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FinFET and preparation method thereof

A substrate and drain technology, applied in the manufacture of semiconductor/solid-state devices, electrical components, circuits, etc., can solve the problems of low on-off speed and high power consumption of devices, and achieve lower power consumption, lower working voltage, and suppression The effect of the short channel effect

Pending Publication Date: 2019-07-05
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Abstract
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  • Claims
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Problems solved by technology

[0010] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a FinFET and its preparation method, which are used to solve the problems of high operating voltage, high sub-threshold swing, low on-off speed of the device in the prior art and The problem of high power consumption

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  • FinFET and preparation method thereof
  • FinFET and preparation method thereof

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preparation example Construction

[0034] The present invention also includes the preparation method of the FinFET, refer to figure 2 , figure 2 Shown is the flow chart of the preparation method of the FinFET of the present invention. The method at least includes the following steps:

[0035] Step 1, providing a silicon substrate, doping P-type ions in the silicon substrate to form the base 01; that is to say, the formation of the P-type base is by implanting P-type ions into the silicon material plate, so as to form figure 1 P-type substrate 01 shown.

[0036] Step 2. Etching the base to form protrusions of source and drain interconnected vertically;figure 1 Shown is a schematic diagram of the cross-sectional structure of the FinFET, therefore, the source and drain bumps can only be figure 1 presented in the form of cross-sections. The source and drain protrusions serve as the source and drain of the FinFET;

[0037] Step 3, forming a silicon dioxide layer 03 on the upper surface of the substrate 01 and...

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Abstract

The invention provides a FinFET and a preparation method thereof. The method comprises the steps of: doping P-type ions in a silicon substrate; etching the substrate to form source and drain bulges which are connected with each other; forming silicon dioxide layers at the upper surface of the substrate and on two sides of the connection of the source and drain bulges; depositing a high dielectriclayer, a piezoelectric material layer and a titanium nitride layer at the connection across the source and drain bulges; doping and annealing the source and drain bulges; forming a ferroelectric material layer on the titanium nitride layer and performing annealing; and depositing a tantalum nitride layer on the ferroelectric material layer. The objective of the invention is to introduce a ferroelectric material and a piezoelectric material into a gate based on the FinFET, integrate with the existing FinFET manufacture process and employ the negative capacitance effect of the ferroelectric material and the electrostriction effect of the piezoelectric material to commonly achieve the voltage amplification function. The working voltage of the device is reduced, the subthreshold swing amplitude is reduced, the on / off speed of the device is improved, further, the working power consumption is reduced, the short-channel effect is effectively inhibited, the power consumption is reduced, and the cost is reduced.

Description

technical field [0001] The invention relates to the field of design and manufacture of semiconductor devices, in particular to a FinFET and a preparation method thereof. Background technique [0002] In traditional integrated circuits, a large part of the working heat comes from the switching process of the device's on-off state. Under the same operating frequency, the faster the switching speed, the smaller the power consumption. An important parameter reflecting the switching speed is the sub-threshold swing. The smaller the value of the sub-threshold swing, the lower the power consumption. At present, a conventional field effect transistor requires at least a 60mV gate voltage change at room temperature to produce an order of magnitude current change, that is, the subthreshold swing is not less than 60mV / decade (an order of magnitude). [0003] At present, the sub-threshold swing value is reduced by adjusting the gate oxide layer structure and thickness composition, cha...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/51H01L21/336
CPCH01L29/785H01L29/513H01L29/516H01L29/518H01L29/517H01L29/66795
Inventor 陕皓
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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