Preparation method of silicon epitaxial wafer for high-voltage power device

A high-voltage power device, silicon epitaxial wafer technology, applied in semiconductor/solid-state device manufacturing, electrical components, gaseous chemical plating, etc., can solve the problems of high defect density, discrete thickness distribution, uncontrolled resistivity, etc. The effect of reducing the disturbance effect of resistivity and reducing the high temperature heating time

Active Publication Date: 2019-10-25
CHINA ELECTRONICS TECH GRP NO 46 RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to overcome the existing problems of discrete thickness distribution, out-of-control resistivity and high defect density in the preparation process of silicon epitaxial wafers for high-voltage power devices, and to develop a method for preparing silicon epitaxial wafers for high-voltage power devices.

Method used

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  • Preparation method of silicon epitaxial wafer for high-voltage power device
  • Preparation method of silicon epitaxial wafer for high-voltage power device
  • Preparation method of silicon epitaxial wafer for high-voltage power device

Examples

Experimental program
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Effect test

Embodiment 1

[0032] (1) Heat the base of the reaction chamber, set the temperature to 1180 °C, flow in hydrogen chloride gas for etching, set the flow rate to 18 L / min, and set the etching time to 240 sec. The residual substances deposited in the early stage of the base were removed by etching, and then the reaction chamber was purged with a large flow rate of 90 L / min hydrogen to remove the impurities etched from the base from the reaction chamber, and then the base was cleaned. Cool down to 60°C.

[0033] (2) Install the silicon substrate on the base of the reaction chamber, raise the temperature of the silicon substrate to 1180 °C, and introduce low-flow hydrogen chloride gas into the reaction chamber, set the flow rate of hydrogen chloride to 0.8 L / min, and set the polishing time to 15 sec, the surface of the silicon substrate is polished.

[0034] (3) The reaction chamber was purged with a large flow rate of 90 L / min of hydrogen, and the purge time was set at 5 min to remove the impu...

Embodiment 2

[0043] (1) Heat the base of the reaction chamber, set the temperature to 1180 °C, flow in hydrogen chloride gas for etching, set the flow rate to 18 L / min, and set the etching time to 240 sec. The residual substances deposited in the early stage of the base were removed by etching, and then the reaction chamber was purged with a large flow rate of 90 L / min hydrogen to remove the impurities etched from the base from the reaction chamber, and then the base was cleaned. Cool down to 60°C.

[0044] (2) Install the silicon substrate on the base of the reaction chamber, raise the temperature of the silicon substrate to 1160 °C, and introduce low-flow hydrogen chloride gas into the reaction chamber, set the flow rate of hydrogen chloride to 1.0 L / min, and set the polishing time to 15 sec, the surface of the silicon substrate is polished.

[0045] (3) The reaction chamber was purged with a large flow rate of 90 L / min of hydrogen, and the purge time was set at 5 min to remove the impu...

Embodiment 3

[0054] (1) Heat the base of the reaction chamber, set the temperature to 1180 °C, flow in hydrogen chloride gas for etching, set the flow rate to 18 L / min, and set the etching time to 240 sec. The residual substances deposited in the early stage of the base were removed by etching, and then the reaction chamber was purged with a large flow rate of 90 L / min hydrogen to remove the impurities etched from the base from the reaction chamber, and then the base was cleaned. Cool down to 60°C.

[0055] (2) Install the silicon substrate on the base of the reaction chamber, raise the temperature of the silicon substrate to 1160°C, inject low-flow hydrogen chloride gas into the reaction chamber, set the flow rate of hydrogen chloride to 1.2 L / min, and set the polishing time to 15 sec, the surface of the silicon substrate is polished.

[0056] (3) The reaction chamber was purged with a large flow rate of 90 L / min of hydrogen, and the purge time was set at 5 min to remove the impurities v...

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Abstract

The invention discloses a preparation method of a silicon epitaxial wafer for a high-voltage power device. According to the method, a reaction cavity of the epitaxial equipment is purified and the content of impurities accumulated in the cavity is reduced by long-time purging of large-flow hydrogen before epitaxial growth; the nonlinear gradient heating is adopted, so that the stress accumulated in the heating stage is released in time, and the generation probability of defects is reduced; and the reaction rate is significantly improved by shortening the distance between a quartz bell jar anda base of the reaction cavity of the epitaxial equipment and adopting a large-flow trichlorosilane and hydrogen proportioning mode, and high-speed epitaxial growth is realized under the premise of ensuring good crystallization quality of the silicon epitaxial wafer. The problem of comprehensive control on thickness, resistivity and crystallization quality in the existing preparation process is overcome by adopting the method of sectional growth of the silicon epitaxial wafer layer. the prepared silicon epitaxial wafer has a bright surface, is free from dislocation, staggered layers, slip linesand fog defects, realizes the controllability of material indexes such as thickness, resistivity and defects and meets the use requirements of the high-voltage power device.

Description

technical field [0001] The invention relates to the preparation technology of semiconductor epitaxial materials, in particular to a preparation method of silicon epitaxial wafers for high-voltage power devices. Background technique [0002] At present, with the rapid development of microwave, electric power and optoelectronic systems in the direction of high response speed, high sensitivity, and high integration, there is an urgent need for high-quality high-voltage power devices, because each system component needs to embed hundreds of power devices , the failure of a single device will cause non-negligible interference to the working state of the whole machine system, so the quality characteristics of the silicon epitaxial wafer used as the substrate are becoming more and more stringent. Since the working environment of high-voltage power devices determines the properties of thick layers of silicon epitaxial wafers with high resistance and low defects, it is generally requ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02C23C16/24
CPCC23C16/24H01L21/02381H01L21/02532H01L21/02658H01L21/02664
Inventor 周幸李明达王楠赵扬李普生
Owner CHINA ELECTRONICS TECH GRP NO 46 RES INST
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