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Silicon wafer with silicon oxide film on surface and preparation method

A technology of silicon oxide and thin film, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as difficult insulating layers, reduce reaction temperature, prevent adverse effects, and expand application prospects

Inactive Publication Date: 2020-03-24
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the electrochemical method at room temperature is difficult to achieve a controllable thickness of the insulating layer in the microchannel with a large aspect ratio.

Method used

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  • Silicon wafer with silicon oxide film on surface and preparation method
  • Silicon wafer with silicon oxide film on surface and preparation method
  • Silicon wafer with silicon oxide film on surface and preparation method

Examples

Experimental program
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Embodiment 1

[0044] see figure 1 , Figure 2a to Figure 2c Shown, the invention provides a kind of preparation method of the silicon chip that the surface has silicon oxide thin film, it comprises the steps:

[0045] A1: Provide a silicon substrate 1, the surface of the silicon substrate 1 is provided with vertical blind holes or through holes, and the aspect ratio of the blind holes or through holes is 1:1~1:10;

[0046]A2: Preparation of the precursor of the porous layer on the surface of the silicon substrate: cover the other surface of the silicon substrate that does not need to be etched with polyimide tape, and then place the silicon substrate 1 in the etching solution, The outer surface in contact with the etching solution provides fluoride ions, and at room temperature, the surface of the silicon substrate 1 and the walls of the blind holes are etched by electrolysis to form a porous layer 2. In this embodiment, the composition of the etching solution is Ethanol and fluorine-cont...

Embodiment 2

[0059] This embodiment provides a method for preparing a silicon wafer with a silicon oxide film on the surface. The aspect ratio of the blind hole is selected to be 1:5, and the resistivity is 10. -2 Ω silicon substrate; the specific steps are as follows:

[0060] Step 1: Under the condition of 25°C, use acetone, alcohol and deionized water to ultrasonically clean the silicon wafer for 5 minutes respectively, take it out and dry it for later use;

[0061] Step 2: Prepare an etching solution. In this embodiment, the etching solution is composed of ethanol and a fluorine-containing reagent, wherein the fluorine-containing reagent is preferably a hydrofluoric acid reagent. Add 250 mL of 95% pure absolute ethanol into a polytetrafluoroethylene container, then add 50 mL of 40% hydrofluoric acid solution under magnetic stirring, stir for 20 minutes and let stand to obtain a clear solution.

[0062] Step 3: After the silicon substrate cleaned in step 1 is covered with polyimide tap...

Embodiment 3

[0067] This embodiment provides a method for preparing a silicon wafer with a silicon oxide film on the surface, using a silicon substrate with a blind hole aspect ratio of 1:10 and a resistivity of 20Ω; the specific steps are as follows:

[0068] Step 1: Under the condition of 25°C, use acetone, alcohol and deionized water to ultrasonically clean the silicon wafer for 5 minutes respectively, take it out and dry it for later use;

[0069] Step 2: Prepare an etching solution. In this embodiment, the etching solution is composed of ethanol and a fluorine-containing reagent, wherein the fluorine-containing reagent is preferably a hydrofluoric acid reagent. Add 250 mL of 95% pure absolute ethanol into a polytetrafluoroethylene container, then add 50 mL of 40% hydrofluoric acid solution under magnetic stirring, stir for 20 minutes and let stand to obtain a clear solution.

[0070] Step 3: After the silicon substrate cleaned in step 1 is covered with polyimide tape, the part of the ...

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Abstract

The invention discloses a preparation method of a silicon wafer with a silicon oxide film on the surface, which comprises the following steps: providing a silicon substrate, and arranging vertical blind holes or through holes on the surface of the silicon substrate; preparing a porous layer on the surface of the silicon substrate and the hole wall of the blind hole or the through hole through an electrolytic method; and finally, forming a silicon oxide film on the porous layer through an electrolytic method. Through firstly corroding a porous layer on the surface of a silicon substrate and thehole wall of a blind hole or a through hole to serve as a precursor reactant of silicon oxide, the reaction temperature of follow-up oxidation reaction is greatly reduced. Compared with a traditionalvapor deposition technology with the lowest reaction temperature of 150 DEG C, the reaction temperature can be reduced to the room temperature, the application prospect is effectively expanded, and the silicon oxide insulating layer with the controllable thickness is prepared in the micro-channel with the large depth-to-width ratio.

Description

technical field [0001] The invention belongs to the field of semiconductor material preparation, in particular to a silicon chip with a silicon oxide film on its surface and a preparation method. Background technique [0002] Semiconductor through-hole interconnection technology has high integration density and relatively mature process conditions, and can be widely used in 3D packaging, and has become one of the most important packaging forms in the future. In the semiconductor microchannel insulating layer preparation technology, the existing insulating layers mainly include inorganic insulating layers such as silicon oxide and silicon nitride, and organic insulating layers. Inorganic insulating layers have the advantages of high breakdown voltage, small dielectric loss, high hardness, and wear resistance, and have great application prospects in semiconductor manufacturing. [0003] The preparation methods of the inorganic insulating layer mainly include the traditional t...

Claims

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Application Information

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IPC IPC(8): H01L21/02
CPCH01L21/02164H01L21/02238
Inventor 段浩泽文紫妍李明
Owner SHANGHAI JIAO TONG UNIV
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