Device for read-write control based on time division multiplexing in DDR3

Abstract

In order to solve the problem that read-write control of a DDR3 over different signals needs to be reasonably achieved in order to achieve data storage and conversion of multiple paths of independentsignals on one DDR3, the invention provides a device for read-write control based on time division multiplexing in DDR3. The device comprises a time division multiplexing module, a DDR3 write controlstate machine module, a DDR3 read control state machine module, a DDR3 read-write data module, a DDR3 read-write address module and a read-write command signal generation module. The time division multiplexing module is used for generating exclusive read time slots and write time slots of independent signals, and the read and write processes of the paths of signals are completely independent; theDDR3 read and write control state machine modules are used for controlling the data reading and writing processes of the DDR3 respectively; and the DDR3 read-write data, address and read-write commandsignal generation modules are used for completing the most direct data interaction process with the DDR3. The hardware implementation structure is simple, flexible and configurable, the implementation cost can be reduced, and the system operation frequency can be improved under certain conditions.

Description

technical field [0001] The invention relates to the read-write control technology of DDR3 memory, in particular to the technology of time-division multiplexing read-write control in DDR3. Background technique [0002] The improvement of human needs in various aspects has promoted the development of science and technology. As the double-rate synchronous dynamic memory DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), which is widely used in memory, it has also developed rapidly. Due to the high speed of DDR3, low power consumption, low heat generation and relatively low cost, DDR3 is currently widely used on FPGA development boards. The use of DDR3 in FPGA implementation, on the one hand, is to store large-capacity data to reduce the consumption of storage resources in the FPGA chip; the other is to use the high speed of DDR3 to improve the data throughput rate of the system and reduce processing delay time. In addition, DDR3 can also conveniently transf...

AI Technical Summary

Problems solved by technology

[0003] Due to the improvement of technical requirements, it is often necessary to process multiple signal data on one chip in some hardware implementations. For example, for a wireless communication system that needs to support multi-user access and support multiple information rates, its baseband processing needs to be processed in FPGA In order to improve the resource consumption problem caused by multi-channel signals, DDR3 will be considered to store the intermediate processed data at this time, but based on the consideration of cost and DDR3 storage characteristics, when it is necessary to process multiple independent signals, DDR Only one signal can be supported for reading or writing at the same time

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