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Micro-LED chip structure capable of reducing side wall defect recombination and preparation method

A chip structure and defect technology, applied in the direction of electrical components, circuits, semiconductor devices, etc., can solve the problem of Micro-LED luminous efficiency and uniformity, increase the conductivity of the middle position of the ITO layer, and prevent current from being bound in the middle of the device Area and other issues, to achieve the effects of reducing optical crosstalk effects, improving lateral confinement, and reducing non-radiative recombination effects

Pending Publication Date: 2021-01-22
天津赛米卡尔科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For example, using atomic layer deposition technology combined with wet etching process, it is found that the damage caused by etching to the ITO layer or p-GaN layer can be reduced to a certain extent, the side wall damage effect can be alleviated, and the photoelectric performance of Micro-LED has been improved. Not only the luminous intensity is more uniform, but the current leakage is significantly reduced, but this does not completely solve the problem of Micro-LED luminous efficiency and uniformity (Wong M S, et al. High efficiency of III-nitride micro-light-emitting diodes by sidewall passivation using atomiclayer deposition[J]. Optics Express, 2018, 26); the Chinese patent No. CN202010401581.5 discloses a preparation method, structure and display terminal of a Micro-LED chip. Bombardment increases the conductivity in the middle of the ITO layer, while the surrounding conductivity is low, effectively avoiding the leakage phenomenon, current congestion effect and thermal effect caused by the large upper and lower conductivity of the edge area, and improving the luminous efficiency, but this method is complicated. Moreover, ITO is originally a good N-type semiconductor. Even if the local conductivity is improved through oxygen ion bombardment, it cannot cause a significant potential difference between the middle and edge positions of ITO, and cannot effectively confine the current to the middle region of the device.

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  • Micro-LED chip structure capable of reducing side wall defect recombination and preparation method
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  • Micro-LED chip structure capable of reducing side wall defect recombination and preparation method

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preparation example Construction

[0045]The present invention is a method for preparing a novel Micro-LED chip structure with reduced sidewall defects. The steps of the method are as follows:

[0046]In the first step, the substrate 101 is cleaned with acetone, absolute ethanol, and deionized water in sequence in ultrasound, and the substrate 101 is cleaned by ultrasound for 5-10 minutes each time to remove foreign matter attached to the surface of the substrate 101;

[0047]In the second step, in the MOCVD or MBE reaction furnace, a buffer layer 102 with a thickness of 0.01 μm to 0.05 μm is epitaxially grown on the surface of the substrate 101 processed in the first step to realize the nucleation layer and release the lattice distortion. The stress caused by the distribution;

[0048]In the third step, in a MOCVD or MBE reaction furnace, a non-doped N-type semiconductor material layer 103 with a thickness of 2 μm-6 μm is epitaxially grown on the buffer layer 102 obtained in the second step at a high temperature to achieve t...

Embodiment 1

[0057]The present embodiment is a novel Micro-LED chip structure with reduced sidewall defect recombination. The epitaxial structure includes in order along the epitaxial growth direction: a substrate 101, a buffer layer 102, an undoped semiconductor material layer 103, and an N-type semiconductor material Layer 104, multiple quantum well layer 105, P-type confinement layer 106, P-type semiconductor material layer 107, P-type heavily doped semiconductor material layer 108, N-type material transport layer 109, P-type ohmic electrode 110, and N-type ohmic electrode 111 . Among them, the lateral size of the chip is 10 μm, the material of the N-type material transfer layer 109 is indium tin oxide, and the P-type heavily doped semiconductor material layer 108 is located in the middle area above the P-type semiconductor material layer 107, which occupies the P-type semiconductor material layer 107. 80% of the area, the N-type material transmission layer 109 directly contacts the P-type se...

Embodiment 2

[0076]The present embodiment is a novel Micro-LED chip structure with reduced sidewall defect recombination. The epitaxial structure includes in order along the epitaxial growth direction: a substrate 101, a buffer layer 102, an undoped semiconductor material layer 103, and an N-type semiconductor material Layer 104, multiple quantum well layer 105, P-type confinement layer 106, P-type semiconductor material layer 107, P-type heavily doped semiconductor material layer 108, N-type material transport layer 109, P-type ohmic electrode 110, and N-type ohmic electrode 111 . Among them, the lateral size of the chip is 30 μm, the material of the N-type material transport layer 109 is indium tin oxide, and the P-type heavily doped semiconductor material layer 108 is located in the middle area above the P-type semiconductor material layer 107, which occupies the P-type semiconductor material layer 107. 90% of the area, the N-type material transfer layer 109 directly contacts the P-type semic...

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Abstract

The invention discloses a micro-LED chip structure capable of reducing side wall defect recombination and a preparation method. According to the invention, the structure among a P-type semiconductor material layer, a P-type heavily doped semiconductor material layer and an N-type material transmission layer of the chip structure is changed on the basis of a conventional Micro-LED chip structure. Wherein the P-type heavily-doped semiconductor material layer is only located in the middle area above the P-type semiconductor material layer, the N-type material transmission layer completely coversthe P-type semiconductor material layer and the P-type heavily-doped semiconductor material layer, and the N-type material transmission layer is in direct contact with part of the P-type semiconductormaterial layer; the structure provided by the invention utilizes a reverse bias junction formed by the N-type material transmission layer and the P-type semiconductor material layer at the contact interface to deplete holes in the P-type semiconductor material layer, thereby reducing the non-radiative recombination effect of the side wall region of the chip, improving the lateral limiting effectof the injection current, therefore, the optical crosstalk effect between display pixel points is reduced.

Description

Technical field[0001]The invention relates to a novel Micro-LED chip structure with reduced sidewall defects and a preparation method, in particular to a preparation method of a high-power miniature semiconductor light-emitting diode, belonging to the technical field of semiconductor optoelectronic devices.Background technique[0002]With the continuous innovation and development of display technology, the size of each pixel display unit is continuously reduced, and Micro-LED display technology emerged as the times require, inheriting the high efficiency, high brightness, high reliability and fast response time of inorganic LEDs. It has the characteristics of self-luminous light without a backlight, and has the advantages of energy saving and environmental protection, simple structure, small size, light and thin devices. It is expected to be applied to augmented reality miniature projection devices and car head-up display projections that require high brightness, and expand to many fi...

Claims

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Application Information

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IPC IPC(8): H01L33/06H01L33/14H01L33/00
CPCH01L33/007H01L33/06H01L33/14
Inventor 寇建权
Owner 天津赛米卡尔科技有限公司
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