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Gallium nitride wafer material containing insulating substrate and preparation and application thereof

A technology of gallium nitride wafers and insulating substrates, which is used in semiconductor/solid-state device manufacturing, electrical components, and electrical solid-state devices. Heat generation and power dissipation, the effect of reducing parasitic effects

Pending Publication Date: 2021-10-26
SOUTH CHINA NORMAL UNIVERSITY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] As one of the representatives of the third-generation semiconductor materials, GaN has the advantages of high electron mobility, high temperature resistance, radiation resistance, wide direct band gap, and good physical and chemical stability. It can be used in high-voltage, high-frequency power The preparation of electronic devices provides a new direction for high data rate, ultra-fast response integrated circuit systems, but there is a gap between the existing GaN-based optoelectronic devices and the traditional Si-based optoelectronic devices (integrated on SOI wafers). and problems such as the inability to integrate in a small size

Method used

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  • Gallium nitride wafer material containing insulating substrate and preparation and application thereof
  • Gallium nitride wafer material containing insulating substrate and preparation and application thereof
  • Gallium nitride wafer material containing insulating substrate and preparation and application thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0090] refer to figure 2 , prepare the GOI wafer material by the following steps:

[0091] Using the MOCVD method, a 500nm-thick undoped GaN buffer layer (growth conditions: 480°C, 40Torr) was sequentially grown on a sapphire substrate, with a thickness of 1.5μm and a Si doping concentration of 1×10 19 cm -3 GaN sacrificial layer (growth condition: 980°C, 40Torr), 500nm thick undoped single crystal GaN layer (growth condition: 980°C, 40Torr), to obtain the basic sample with epitaxial structure;

[0092] Weigh 4g of polyvinyl alcohol and mix it with 21ml of deionized water, stir magnetically for more than 8 hours to form PVA glue; apply the prepared PVA glue onto the Si substrate (substrate 1), and apply the PVA glue on the Si substrate The bottom is reversed to the upper surface (+c surface) of the single crystal GaN layer, and heated on a hot stage at 50°C for 10 minutes to complete the bonding;

[0093] The bonded sample was fixed to the anode of the electrolytic cell, a...

Embodiment 2

[0097] refer to image 3 , prepare the GOI wafer material by the following steps:

[0098] Using the MOCVD method, a 500nm-thick undoped GaN buffer layer (growth conditions: 480°C, 40Torr) was sequentially grown on a sapphire substrate, with a thickness of 1.5μm and a Si doping concentration of 1×10 19 cm -3 GaN sacrificial layer (growth condition: 980°C, 40Torr), 500nm thick undoped single crystal GaN layer (growth condition: 980°C, 40Torr), to obtain the basic sample with epitaxial structure;

[0099] Spin-coat a layer of photoresist with a thickness of 2 μm on the upper surface of the single crystal GaN layer to obtain a photoresist layer; expose the photoresist layer to the photoresist layer with a pattern mask designed in advance, and then put it into the developer Developing and drying to obtain a sample containing a graphic mask;

[0100] Using the pattern as a mask, the single crystal GaN layer was etched by ICP with an etching depth of 300nm, and the etched product...

Embodiment 3

[0108] The single crystal GOI wafer is prepared by the same process as in Example 1, the difference is that the substrate 1 uses a flexible substrate material, such as a polyethylene terephthalate substrate or a copper foil substrate, and simultaneously does not use The process of substrate 1 is used as a comparison, and can be obtained as attached Figure 5-6 The schematic diagram of the integrity of the single-crystal GaN layer is shown. It can be seen that the use of Si substrates or flexible substrates can effectively reduce the phenomenon of cracking, curling, and folding of the single-crystal GaN layer during the electrochemical corrosion process. The effect of the substrate is the best, and finally the best quality single crystal layer can be obtained, so that the product has excellent crystallinity and surface quality.

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Abstract

The invention discloses a gallium nitride wafer material containing an insulating substrate and preparation and application thereof, and the preparation comprises the steps: obtaining a base material containing a base substrate, and a single crystal gallium nitride (GaN) layer and an intermediate functional layer which are obtained on the base substrate through epitaxial growth, and then sequentially bonding the base material with a first substrate, peeling off the base substrate and the middle functional layer, adding an insulating layer to the surface of gallium nitride, bonding a second substrate to the surface of gallium nitride, removing the first substrate, and obtaining the gallium nitride wafer. The wafer material has excellent small-size integration capacity, higher data processing and transmission capacity, higher anti-interference capacity and lower heat production and power consumption; and the overall performance is superior to that of a traditional Si-based photoelectric material with an SOI wafer as a carrier.

Description

technical field [0001] The invention relates to the technical field of semiconductor materials, in particular to the technical field of gallium nitride materials. Background technique [0002] Today, with the rapid development of informatization, people have put forward higher requirements for the speed of hardware processing and information transmission. Under the guidance of Moore's Law, the size of semiconductor devices is constantly shrinking, and the integration level of integrated circuits is constantly increasing. However, as the size of devices shrinks to the (sub) nanometer level, Moore's Law begins to fail, problems such as parasitic effects and high power consumption emerge one after another, and integrated circuits have entered a bottleneck period of development. The preparation of silicon-on-insulator (SOI) wafers, on the one hand, realizes the isolation between various devices in integrated circuits; on the other hand, it also significantly reduces parasitic e...

Claims

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Application Information

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IPC IPC(8): H01L21/762H01L27/12
CPCH01L21/76251H01L27/1203
Inventor 王幸福董建奇陈鑫
Owner SOUTH CHINA NORMAL UNIVERSITY