Laminated cell based on back contact and preparation method thereof
A stacked battery and back contact technology, applied in circuits, photovoltaic power generation, electrical components, etc., can solve the problems of poor cost performance and high unit price of low-temperature silver paste consumption, so as to prevent leakage and parasitic parallel resistance, reduce the cost of electricity, The effect of reducing consumption
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Embodiment 1
[0079] The invention provides a kind of MWT type perovskite HJT laminated battery product, refer to figure 1 with figure 2 , which includes from top to bottom: front gate electrode, front TCO, top electrode buffer layer, electron transport layer, perovskite light absorbing layer, hole transport layer, tunneling layer (ITO), N+ type doped amorphous Silicon layer n+-Si(a), first intrinsic amorphous silicon passivation layer i-Si(a), N-type single crystal silicon substrate n-Si(c), second intrinsic amorphous silicon passivation layer i-Si(a), p-type doped amorphous silicon layer p-Si(a), back TCO layer, back gate wire electrode.
Embodiment 2
[0081] The invention provides a kind of MWT type perovskite HJT laminated battery product, refer to figure 1 with figure 2 , which includes from top to bottom: front grid electrode, front TCO, top electrode buffer layer, electron transport layer, perovskite light absorbing layer, hole transport layer, tunneling layer (In 2 o 3 ), N+-type doped amorphous silicon layer n+-Si(a), the first intrinsic amorphous silicon passivation layer i-Si(a), N-type single crystal silicon substrate n-Si(c), the second Intrinsic amorphous silicon passivation layer i-Si(a), p-type doped amorphous silicon layer p-Si(a), back TCO layer, and back gate electrode.
Embodiment 3
[0083] The invention provides a kind of MWT type perovskite HJT laminated battery product, refer to figure 1 with figure 2 , which includes from top to bottom: front gate electrode, front TCO, top electrode buffer layer, electron transport layer, perovskite light-absorbing layer, hole transport layer, tunneling layer (p+ / n+ double-layer silicon film composition Tunneling junction), N+ type doped amorphous silicon layer n+-Si(a), first intrinsic amorphous silicon passivation layer i-Si(a), N-type single crystal silicon substrate n-Si(c ), a second intrinsic amorphous silicon passivation layer i-Si(a), a p-type doped amorphous silicon layer p-Si(a), a back TCO layer, and a back gate line electrode.
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