Manufacturing method for multichip module

Abstract

A manufacturing method for a multi-chip module is provided, which is designed to pack two or more semi-conductor chips in a stacked manner over a chip carrier in a single package. An adhesive with fillers allows a second chip to be superimposed over a first chip after the first chip is electrically connected to the chip carrier. The diameter of the fillers is higher than loop height of the bonding wires that are positioned above the active surface of the first chip to prevent the bonding wires to come in contact with the second chip. Moreover, the other embodiment of the fillers (such as copper or aluminum) with high thermal conductivity is also capable of enhancing heat dissipation of the stacked package application.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) [0001] This is a Divisional of co-pending application Ser. No. 10 / 454,158 filed Jun. 3, 2003, which is hereby incorporated by reference herein.FIELD OF THE INVENTION [0002] The present invention relates to multichip modules (MCM) and a manufacturing method thereof, and more particularly to a multichip module having more than two chips disposed on a chip carrier in a stacked manner and a manufacturing method thereof. BACKGROUND OF THE INVENTION [0003] With increasing demands for higher electronic performances and miniaturization, multichip modules have become a trend. A multichip module is a module having at least 2 chips adhered onto a single chip carrier such as a substrate or a leadframe. The chip-to-chip carrier bonding manner can be generally categorized into two methods. One method is by spacing chips next to each other on a chip carrier. This bonding method essentially would not increase the overall height of the semiconductor package,...

AI Technical Summary

Benefits of technology

[0011] A primary objective of the present invention is to provide a multichip module and a manufacturing method thereof, which simplifies and reduces the time for the manufacturing procedures as well as reducing the overall manufacturing cost. Another objective of the present invention is to provide a multichip module and a manufacturing method thereof, in which the differences in coefficient of thermal expansion between the topmost, bottommost chip and that of the adhesive layer interposed in between are greatly reduced so as to prevent delamination at the chip bonding surface, chip cracking or broken wires, which ultimately enhances the yield for the packaged product. Further, another objective of the present invention is to provide a multichip module and a manufacturing method thereof in which the heat dissipating efficiency of the topmost and bottommost chip is enhanced, thereby solving the heat retaining problem. Yet another objective of the present invention is to provide a multichip module and a manufacturing method thereof, in which the fluidity of the adhesive is reduced, allowing a preferred planarity of the topmost chip adhered onto the adhesive layer to be maintained. Yet another objective of the present invention is to provide a multichip module and a manufacturing method thereof, in which the chips have no size limitation. Further another objective of the present invention is to provide a multichip module and a manufacturing method thereof, in which the thickness of the adhesive layer interposed can be reduced, thereby reducing the overall height of the packaged product. Further, another objective of the present invention is to provide a multichip module and a manufacturing method thereof, in which the topmost chip cannot make contact with the bottommost chip, thereby eliminating broken wires and short-circuits.

[0015] Yet, in another embodiment of the present invention, reverse bonding technique is utilized to substantially reduce the loop height of the first bonding wires, allowing fillers with smaller diameters to be used, so as to reduce the thickness of the adhesive, and thereby achieving the objective of reducing the overall height of a semiconductor package.

[0017] The fillers can be made by dielectric polyimide, copper, aluminum, other alloys or other stiff and conductive materials. Addition of fillers into adhesive could change the characteristics of the adhesive, which in turn reducing the coefficient of thermal expansion of the adhesive thereby reducing thermal stress difference between the adhesive, chip and bonding wires, preventing the wire bonding surface from delamination, chip cracking or even broken wires. Moreover, addition of solid fillers into adhesive can effectively reduce the fluidity of the adhesive, which, in turn prevents movement of the second chip after mounting on the adhesive layer, and thereby a preferred planarity can be achieved. Fillers made by metal materials could also enhance the heat dissipation of the chip, thereby solving a heat-retaining problem for the stacked multichip structure.

Problems solved by technology

This bonding method essentially would not increase the overall height of the semiconductor package, but the chip carrier must contain a large die attachment area to accommodate the required number of chips.

This increased chip carrier surface will generate a higher thermal stress, and therefore result in a warpage of the chip carrier.

This increases the possibility of delamination at the interface between the chip and the chip carrier, making reliability more of a concern.

In such a case, the top-most chip would have the smallest size, that is, the surface for disposing electronic circuits and electronic elements is reduced, which is disadvantageous for developing high-density integrated circuits.

However, when using insulated tapes made by adhesive materials such as polyimide for adhering the second chip 64, because of the high fluidity the planarity of the second chip 64 is difficult to achieve.

Moreover, because Coefficient of Thermal Expansion (CTE) differences between the adhesive materials and the chip are great during temperature cycles of the latter procedures, the chip bonding surface may easily suffer from warpage, delamination or even chip cracking.

Although the foregoing method can successfully overcome the problem of differences in CTE between the chip and the insulator apparatus, this method is costly and the manufacturing procedures are complex and prolonged, making it difficult to enhance the final yield.

Moreover, since adhesives of high fluidity need to be applied over the active surface of the first chip or the surface of the insulator apparatus prior to bonding between the insulator apparatus and the topmost chip (i.e. the second chip), the adhesives would often lead to movement of the insulator or the topmost chip, or even damage the first chip pads.

However, one drawback is that for the above-mentioned reverse bonding technique, the formation of a plurality of studs on the first chip for wire bonding is required prior to reverse bonding.

This makes the procedures longer and costly.

In addition, as the Coefficient of Thermal Expansion (CTE) between the adhesive and the gold wires is great, the gold wires embedded in the adhesive may be easily broken due to different thermal stress under thermal cycles at latter procedures and as a result, the electronic performances of gold wires may be seriously impaired.

Besides, during bonding of the second chip, highly accurate control equipment must be additionally incorporated to accurately control the bond force of the second chip against the adhesive layer, which further increases the overall manufacturing cost.

Images