Semiconductor device and process for producing the same

Inactive Publication Date: 2005-07-28
OHNISHI KAZUHIRO +1
View PDF5 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0010] An object of the present invention is to provide a semiconductor device with reduced contact resistance between the reaction barrier layer and the polycrystalline silicon in the metal / reaction barrier / polycrystalline silicon-stacked structure, and a process for producing the same.

Problems solved by technology

In the case of high-speed CMOS devices, on the other hand, low threshold voltage and low gate resistance alone are not enough to attain both higher performance and higher integration.
However, the SALICIDE technology is difficult to use together with a self-aligned contact technology and thus is difficult to reduce the layout pitch.
The POLICIDE structure is so high in the sheet resistance that it is difficult to obtain a sufficiently low gate resistance.
This is a problem of the POLICIDE structure.
However, such a stacked structure has a low thermal stability and even if tungsten, i.e. high melting point metal, is used as the metal, reaction takes place between the metal and silicon during the heat treatment at about 650° C., resulting in an increase in resistance, degradation of layer surface state, dielectric breakdown, etc., which are examples of other problems arising.
(2) Device circuit performance is not improved due to the high contact resistance, etc.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device and process for producing the same
  • Semiconductor device and process for producing the same
  • Semiconductor device and process for producing the same

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0043]FIGS. 1A to 1E are cross-sectional views showing process steps for forming a gate electrode according to Example 1 of the present invention.

[0044] Gate insulation layer 102 is formed on the surface of semiconductor substrate 101 e.g., by thermal oxidation, and then polycrystalline silicon layer 103 is deposited thereon e.g. by CVD (FIG. 1A).

[0045] Polycrystalline silicon layer 103 is doped with an impurity of any desired conductivity type (e.g. phosphorus or boron) by ion implanting, followed by activation annealing at 950°-1,000° C. Then, metallic layer 104 of e.g. tungsten is deposited thereon to a thickness of about 5 nm e.g. by sputtering, where precleaning e.g. with hydrofluoric acid is carried out beforehand to remove natural oxide, etc. remaining on the surface of polycrystalline silicon layer 103. Then, metal nitride layer 105 of e.g. tungsten nitride as a reaction barrier and metallic layer 106 of e.g. tungsten are deposited thereon one after the other to a thicknes...

example 2

[0050]FIG. 2A to 2D are cross-sectional views showing process steps for forming a gate electrode according to Example 2 of the present invention.

[0051] The process steps of FIGS. 2A and 2B are identical with those of FIGS. 1A and 1B of Example 1. After gate insulation layer 102, polycrystalline silicon layer 103, metallic layer 104 of e.g. tungsten, metal nitride layer 105 of e.g. tungsten nitride, and metallic layer 106 of e.g. tungsten have been deposited on silicon substrate 101 as a stacked structure (FIG. 26), heat treatment of the stacked structure is carried out at 650° C. or higher in the present Example to react metallic layer 104 with polycrystalline silicon layer 103, thereby forming metal silicide layer 108 of e.g. tungsten silicide only to a thickness about twice as large as that of deposited metallic layer 104 (FIG. 2C) Then, the stacked structure is processed into a gate electrode e.g. by lithography and anisotropic dry etching using a resist (FIG. 2D)

[0052] The gat...

example 3

[0053]FIGS. 3A to 3D are cross-sectional views showing process steps for forming a gate electrode according to Example 3 of the present invention.

[0054] Gate insulation layer 102 is formed on the surface of semiconductor substrate 101 e.g. by thermal oxidation, and then polycrystalline silicon layer 103 is deposited thereon e.g. by CVD (FIG. 3A).

[0055] Polycrystalline silicon layer 103 is doped with an impurity of any desired conductivity type (e.g. phosphorus or boron) by ion implanting, followed by activation annealing at 950°-1,000° C. Then, metal silicide layer 109 of e.g. tungsten silicide is deposited thereon to a thickness of 5-20 nm e.g. by sputtering or CVD, where precleaning e.g. with hydrofluoric acid is carried out beforehand to remove natural oxide, etc. remaining on the surface of polycrystalline silicon layer 103. Then, metal nitride layer 105 of e.g. tungsten nitride as a reaction barrier and metallic layer 106 of e.g. tungsten are deposited thereon one after the o...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Process for producing a semiconductor device includes forming an insulation layer on a semiconductor substrate surface and depositing a silicon layer on the insulation layer, a reaction barrier layer such as a metal nitride layer on the first metallic layer and a second metallic layer on the barrier layer, processing a stacked structure of the silicon layer, first metallic layer, barrier layer and second metallic layer to form a gate electrode, using the gate electrode as a mask and doping an impurity into the surface of the semiconductor substrate to form active regions of the device, heat reacting the first metallic layer with the silicon layer to form a metal silicide layer between the reaction barrier layer and the silicon layer. The heat reaction process effected may be performed prior to or after the formation of the gate electrode. The metal silicide film may be a deposited film.

Description

[0001] This application is a continuation of U.S. application Ser. No. 10 / 812,995, filed Mar. 31, 2004; which, in turn, is a divisional of U.S. application Ser. No. 09 / 829,969, filed Apr. 11, 2001 (now U.S. Pat. No. 6,750,503); and the entire disclosures of which are incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] The present invention relates to a semiconductor device and a process for producing the same and, more particularly, to a semiconductor device with an MIS type transistor and a process for producing the same. [0003] To attain higher performance and higher integration of devices, semiconductor devices have been progressively scaled down over the years, necessitating incorporation of low-resistance materials into the electrode materials. It is thus desirable to incorporate a metal also into the MOS transistor gate electrode. [0004] In the case of high-speed CMOS devices, on the other hand, low threshold voltage and low gate resistance alone are not enough...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/28H01L21/762H01L21/8238H01L29/423H01L29/43H01L29/49H01L29/78
CPCH01L21/28052H01L21/76229H01L29/4941H01L21/823842H01L21/823835H01L21/8234
InventorOHNISHI, KAZUHIROYAMAMOTO, NAOKI
OwnerOHNISHI KAZUHIRO