Electrochemical deposition system

Abstract

A electrochemical deposition system which has a 3-D stacked architecture comprises a factory interface for receiving semiconductor wafers, a mainframe comprising a mainframe transfer robot and a plurality of wafer holder assemblies which disposed on the top thereof, a plurality of electroplating cells disposed within the mainframe, a plurality of cleaning cells disposed within the mainframe and located below the electroplating cells, a plurality of thermal treatment chambers disposed in between the mainframe and the factory interface, and a fluid distribution system fluidly connected to the electroplating cells and the cleaning cells, wherein the mainframe transfer robot transfers the semiconductor wafer from the factory interface and within the electroplating cells, the cleaning cells, and the thermal treatment chambers. As a result, the system of the present invention is expandable to accommodate newly-added processing units without overmuch increased footprint.

Description

FIELD OF INVENTIONThe present invention relates to a system for deposition of a metallic layer onto semiconductor workpieces, more particularly a system for electrochemical or electroless deposition of metallic thin films on semiconductor wafers from electrolyte solutions, chemically etching parts of the deposited films, cleaning the surface of the deposited films and thermally treating the deposited films.RELATED ARTOn-chip interconnects comprises multilayer of metallic wirings embedded in one or more insulating materials on the top of transistor circuit of logic or memory chips. As the circuit density in ultra large scale integrated (ULSI) circuits increases, the size of the features in the pattern of metallic wirings, such as vias and trenches, decreases to submicron level, and the levels of metallization increase. Furthermore, RC delay has become the most dominant effect in degrading the circuit speed as the length of conductive wirings in integrated circuits continues to grow. ...

AI Technical Summary

Benefits of technology

In view of the aforementioned problems, it is an object of the present invention to provide a new architecture of an electrochemical deposition system that may treat larger scale semiconductor wafers with great efficiency to provide high throughput with a small footprint.

Comparing to the system disclosed in the prior art, an advantage of the system of the present invention which has a 3-D stacked architecture is that it has a smaller footprint and may treat larger scale semiconductor wafers with great efficiency to provide high throughput because additional footprint took by some processing cells such as plating cells is saved, and another advantage of the system of the present invention is that it could be expandable to accommodate newly-added processing units without overmuch increased footprint because the newly-added processing units could be disposed on the corresponding layer or layers other than on only one layer as in the prior art, and yet another advantage of the system of the present invention is that it can be serviced and maintained conveniently because the wafer holder assemblies are disposed on the top of the mainframe, eliminating the need of bulky supporting posts which greatly limit tool accessibility, and they can be moved to the corners of the mainframe during user intervention.

The further characteristic of said electrochemical deposition system according to the present invention is that the thermal treatment chamber comprises a heating plate and a heating fluid dispenser for double-side heating the semiconductor wafer, a cooling plate and a cooling fluid dispenser for double-side cooling the semiconductor wafer, at least two wafer holders for receiving the semiconductor wafer and transferring the semiconductor wafer from the heating plate to the cooling plate, and at least two actuators for controlling the movement of the wafer holders. As a result, the system in accordance with the present invention may provide a uniform post electroplating thermal treatment process to improve the electrical and physical properties of the deposited metal films on semiconductor wafers by double-side thermal treating of the wafer, and the thermal treatment chamber could thermally treat multiple wafers simultaneously so that the number of thermal treatment chambers in the mainframe is reduced and throughput of the system of the present invention is increased. And the processing wafer is transferred onto the heating plate in the thermal treatment chamber by the mainframe robot before the beginning of the process and transferred out from the cooling plate in the thermal treatment chamber by the front robot after the process ends. No mainframe / factory-interface hand-off station is needed post processing, so that the robot handoff points are reduced and the transfer efficiency of the system is improved.

The still further characteristic of said electrochemical deposition system according to the present invention is that it may also comprise a vapor phase pre-wet device connected to a vapor generating and delivery system to realize liquid molecules adsorption onto the front surface of a semiconductor wafer that will be processed in the electroplating cell from vapor phase. The adsorbed, or condensed liquid molecules form a thin pre-wetting layer on the front surface of the semiconductor wafer before the semiconductor wafer bearing such a film is put into contact to the electrolyte solution. As a result, the system in accordance with the present invention could provide the reliable process to deposit copper films in ultra-small features on the semiconductor wafer surface without voids caused by incomplete wetting.

Problems solved by technology

Furthermore, RC delay has become the most dominant effect in degrading the circuit speed as the length of conductive wirings in integrated circuits continues to grow.

While copper is good for interconnect metallization, it poses many challenges to metallization during device fabrication.

The main challenge for copper implementation is the deposition system to uniformly fill trench and via features without voids and seams across the entire semiconductor substrate, known as wafer, in a damascene process, or frequently dual damascene process at acceptable manufacture flow cost.

The locations of the processing cells, spin-rinse-dry and bevel etch chambers and the probably added units are designed in one plane, and such a design takes large clean room space for providing satisfactory throughout to meet the demands of the processing system.

Because such a system utilizes a 2-D architecture with all process units placed on one plane, while it is expanded to accommodate newly added process units, the footprint of the system increases, thereby limiting its expandability practically.

These posts are bulky as they must provide stabilization and consistence to the cell head assemblies they support in order to control precisely the movement of the cell head assemblies.

These supporting posts not only take spaces inside the frame enclosure, but also limit the reachability to the mainframe transfer robot, the wafer holder assemblies and the plating cells and make the maintenance of the system inconvenient.

Furthermore, when the dimensions of the vias and trenches in the pattern on a semiconductor wafer become smaller, the features of the wafer become difficult to be completely wetted when the wafer carried by the chuck of the wafer holder assembly immerses into the electrolyte.

This incomplete wetting will lead to defects and voids in the features in the deposited metal films.

But pre-wetting by liquid rinse still cannot wet very small features completely, and the rinse liquid may dilute the plating electrolyte both globally in a high volume factory and locally, leading to new problems.

So these disclosed methods still cannot completely solve the problem of incomplete wetting without significantly introducing process variation and adding manufacturing cost.

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