Silicon carbide substrate, semiconductor device and method for manufacturing silicon carbide substrate

Abstract

There is provided a silicon carbide substrate composed of silicon carbide, including encapsulated regions inside, which form incoherent boundaries between the silicon carbide and the encapsulated regions, wherein propagation of stacking faults in the silicon carbide is blocked.

Description

TECHNICAL FIELD[0001]The present invention relates to a silicon carbide substrate used for a high performance semiconductor device. Particularly, there is provided a silicon carbide substrate which has an extremely low planar defects density on a specific crystal surface, and which can be preferably utilized as a material of a power semiconductor device having high efficiency and high breakdown voltage.DESCRIPTION OF RELATED ART[0002]Silicon carbide has been used as a compound semiconductor material for high performance semiconductor device. However, in some cases, silicon carbide substrate includes high density of crystal defects.[0003]A performance of the semiconductor device is significantly affected by such crystal defects included in the silicon carbide substrate. For example, the representative planar defects, such as an anti-phase boundary and a stacking fault, cause a current leak or dielectric breakdown and remarkably reduce the performance of a power semiconductor device. ...

AI Technical Summary

Benefits of technology

This approach effectively reduces stacking fault density and prevents anisotropic extension, resulting in a substrate with low defect density suitable for high-performance semiconductor applications by blocking fault propagation at incoherent boundaries and absorbing lattice strain.

Problems solved by technology

However, in some cases, silicon carbide substrate includes high density of crystal defects.

A performance of the semiconductor device is significantly affected by such crystal defects included in the silicon carbide substrate.

For example, the representative planar defects, such as an anti-phase boundary and a stacking fault, cause a current leak or dielectric breakdown and remarkably reduce the performance of a power semiconductor device.

Therefore, reduction of such planar defects is the main issue for silicon carbide substrate applicable to the device use.

However, it is insufficient to reduce the stacking faults density only by using this misoriented-Si substrate.

As a result, the effect of annihilation is lost and complete elimination of the stacking faults is not achieved.

This is because the stacking faults exposing the Si-polar face are continuously occurred due to a lattice strain generated during the crystal growth.

One is caused by a temperature distribution in a substrate, and the other is caused by a lattice miss-matching due to annihilation of the stacking faults.

The stacking faults density is actually reduced by using SBE technique, however, complete elimination of the stacking faults is not achieved.

This is because the additional stacking faults occurrence during a SBE growth process, which is mainly caused by the strains existing in the cubic silicon carbide substrate and a homo-epitaxial layer.

Hence, new stacking faults are continuously occurred in the silicon carbide layer to release such strains.

Namely, it is quite difficult to fabricate the cubic silicon carbide substrate having extremely low stacking faults density, which is suitable for manufacture of the high performance device, without controlling the lattice strain generated during the crystal growth.

However, the off-angle is also introduced not only in one direction but also in a direction orthogonal thereto, control of the orientation of the polar-face shown in the aforementioned non-patent document 2 is deteriorated and hence elimination of the anti-phase boundaries is not achieved.

Therefore, the propagation direction of the planar defects cannot be controlled through the growth direction.

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