Data processor and method of processing data

Abstract

A data processor comprises an instruction decode unit (119) for receiving operation codes from an instruction memory (103). A second decoder (114) of the instruction decode unit (119) decodes an operation code for a multiply-add operation, and a second operation unit (117) receives 2 data stored in a register file (115) to perform the multiply-add operation. In parallel with the operations of the second decoder (114) and the second operation unit (117), a first decoder (113) of the instruction decode unit (119) decodes an operation code for 2 data load, and an operand access unit (104) causes 2 data (e.g., n bits each) stored in an internal data memory (105) to be transferred in parallel in the form of combined 2n-bit data to a first operation unit (116). Then, two predetermined registers of the register file (115) store the respective n-bit data from the first operation unit (116).

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to a data processor for high-speed digital signal processing and a method of processing data for high-speed digital signal processing.2. Description of the Background ArtDigital signal processors (DSPs) having an architecture suitable for signal processing have been used as data processors designed specifically for high-speed digital signal processing. These DSPs execute processing frequently used in signal processing such as a multiply-add operation at high speeds. An example of a DSP is Motorola DSP56000. The DSP56000 includes two address pointers, two data memories, and a multiply-add operation unit. Parallel loading of data (e.g., the load of coefficients and data) from two 1-word memories specified respectively by the address pointers, updating of the two address pointers, and the execution of the combined multiply-add operation allows the multiply-add operation to be executed with a high throughp...

AI Technical Summary

Benefits of technology

The parallel processing of the multiply-add operation instruction and the access of two data to the memory allows one multiply-add operation to be performed per clock cycle.

In accordance with the data processor of the ninth aspect of the present invention, a plurality of instructions including the operation code for specifying the application of a memory operand to the register file while updating an address by using the register contents as the address, and the operation code for specifying the execution of the arithmetic operation with reference to the register value are processed by means of pipeline processing technique. This permits the arithmetic operations to be executed without operand interference by means of software, improving the processing performance.

In accordance with the tenth aspect of the present invention, the method of processing data comprises loading the first and second data in parallel from the memory to the r

Problems solved by technology

However, the CPU16 wherein one multiply-add operation requires 12 cycles is difficult to achieve the performance competing with the DSPs (CPU16 Reference Manual, 1993).

This requires the amount of hardware and significantly complicated control.

The PowerPC603 may load a maximum of one word for each clock cycle, resulting in an insufficient supply of operands (Proceedings of COMPCON 1994: "The PowerPC603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor", PowerPC603 RISC Microprocessor User's Manual, 1994).

The DSPs which must include two memories have a complicated memory construction and require very cumbersome data management for d

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