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Data processor and method of processing data

Inactive Publication Date: 2004-12-28
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The simple construction may reduce the costs of the data processor.
In accordance with the data processor of the ninth aspect of the present invention, a plurality of instructions including the operation code for specifying the application of a memory operand to the register file while updating an address by using the register contents as the address, and the operation code for specifying the execution of the arithmetic operation with reference to the register value are processed by means of pipeline processing technique. This permits the arithmetic operations to be executed without operand interference by means of software, improving the processing performance.
It is therefore an object of the present invention to provide an inexpensive high-performance microprocessor-type data processor which readily reduces power consumption under relatively simple control.
It is still another object of the present invention to provide a method of processing data which may achieve high-performance data processing control.

Problems solved by technology

However, the CPU16 wherein one multiply-add operation requires 12 cycles is difficult to achieve the performance competing with the DSPs (CPU16 Reference Manual, 1993).
This requires the amount of hardware and significantly complicated control.
The PowerPC603 may load a maximum of one word for each clock cycle, resulting in an insufficient supply of operands (Proceedings of COMPCON 1994: "The PowerPC603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor", PowerPC603 RISC Microprocessor User's Manual, 1994).
The DSPs which must include two memories have a complicated memory construction and require very cumbersome data management for distribution of data between the two memories.
The use of a 2-port RAM adds to the area and costs of the data processor.
Additionally, the DSP is in general an accumulator machine and is difficult to execute complicated data processing.
However, the microprocessors are not efficient in signal processing unlike the DSPs wherein hardware directly represents the flow of signal processing.
To achieve the DSP-level performance, the state-of-the art microprocessors require an increased amount of hardware, adding to the costs of the data processor.
Further, the microprocessors are difficult to reduce power consumption because of the need for operation at high frequencies.

Method used

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first preferred embodiment

A data processor according to a first preferred embodiment of the present invention will be described below. The data processor of the first preferred embodiment is a 16-bit processor whose addresses and data are 16 bits in length.

FIG. 1 illustrates a set of registers for the data processor of this preferred embodiment. The data processor employs big endian bit and byte ordering wherein the most significant bit is the bit 0.

Sixteen general-purpose registers R0 to R15 are provided for storing data and address values therein. The general-purpose registers R0 to R14 are designated by the numerals 1 to 15 in FIG. 1, respectively. The general-purpose register R13 (designated at 14 in FIG. 1) is allocated as a link (LINK) register for storing a return address for a subroutine jump. The general-purpose register R15 is a register for a stack pointer (SP) including an interruption stack pointer (SPI) 16 and a user stack pointer (SPU) 17. A processor status word (PSW) to be described later sw...

second preferred embodiment

FIG. 28 is a block diagram of a second operation unit 120 for the data processor according to a second preferred embodiment of the present invention corresponding to the second operation unit 117 of the first preferred embodiment. Other units of the data processor of the second preferred embodiment are similar in construction to those of the first preferred embodiment. The second operation unit 120 differs from the second operation unit 117 of the first preferred embodiment in that it includes an ALU 221 operable independently of an adder 231 for performing the multiply-add operation. This allows the execution of the addition and subtraction of the multiply-add / multiply-subtract instructions and other arithmetic and logic operations without interference of hardware.

The ALU 221 performs a 16-bit arithmetic and logic operation. An A2 latch 222 connected to the S4 bus 304 and a B2 latch 223 connected to the S5 bus 305 are input latches for the ALU 221. An ALUO latch 225 is an output la...

third preferred embodiment

FIG. 35 is a functional block diagram of the data processor according to a third preferred embodiment of the present invention. An MPU 850 is an MPU core. An instruction fetch unit 863 and an operand access unit 864 are substantially similar to the instruction fetch unit 102 and operand access unit 104 of the data processor of the first preferred embodiment. The instruction data which are 64 bits in length are applied to the instruction fetch unit 863. The bus interface unit and the like are not shown in FIG. 35.

The MPU core 850 comprises an instruction queue 851, a control unit 852, a register file 860, a first operation unit 858, a second operation unit 859, a third operation unit 861, and a fourth operation unit 862. The instruction queue 851 is an FIFO-controlled instruction buffer for holding a maximum of two 64-bit instructions. The first operation unit 858 includes an incrementor, a decrementor, and an adder and performs management of the PC value, calculation of the branch t...

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Abstract

A data processor comprises an instruction decode unit (119) for receiving operation codes from an instruction memory (103). A second decoder (114) of the instruction decode unit (119) decodes an operation code for a multiply-add operation, and a second operation unit (117) receives 2 data stored in a register file (115) to perform the multiply-add operation. In parallel with the operations of the second decoder (114) and the second operation unit (117), a first decoder (113) of the instruction decode unit (119) decodes an operation code for 2 data load, and an operand access unit (104) causes 2 data (e.g., n bits each) stored in an internal data memory (105) to be transferred in parallel in the form of combined 2n-bit data to a first operation unit (116). Then, two predetermined registers of the register file (115) store the respective n-bit data from the first operation unit (116).

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to a data processor for high-speed digital signal processing and a method of processing data for high-speed digital signal processing.2. Description of the Background ArtDigital signal processors (DSPs) having an architecture suitable for signal processing have been used as data processors designed specifically for high-speed digital signal processing. These DSPs execute processing frequently used in signal processing such as a multiply-add operation at high speeds. An example of a DSP is Motorola DSP56000. The DSP56000 includes two address pointers, two data memories, and a multiply-add operation unit. Parallel loading of data (e.g., the load of coefficients and data) from two 1-word memories specified respectively by the address pointers, updating of the two address pointers, and the execution of the combined multiply-add operation allows the multiply-add operation to be executed with a high throughp...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/302G06F9/32G06F9/34G06F9/355G06F9/38
CPCG06F9/30014G06F9/30072G06F9/30145G06F9/30149G06F9/30167G06F9/30178G06F9/322G06F9/325G06F9/3552G06F9/3822G06F9/3853G06F9/3889G06F9/3893
Inventor MATSUO, MASAHITOYOSHIDA, TOYOHIKO
Owner RENESAS ELECTRONICS CORP
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