The invention relates to the technical field of circuit board analysis, in particular to an
integrated circuit defect
analysis method and
system, and the method comprises the steps: extracting and screening E-
test data of a target product from a
big data platform for
integrated circuit manufacturing; performing defect classification modeling
processing on the screened E-test
test data; calculating a defect
correlation index according to the classification accuracy and the correlation metric value of each candidate E-
test item; determining a defect judgment threshold value and a numerical value distribution direction related to the defect based on a logic regression classifier result of the key
test item, and generating a binary defect
distribution diagram corresponding to each jointed board; calculating the image similarity between the bad jointed board graph and each good jointed board graph; judging whether the image similarity is higher than a preset threshold value or not, and adding the jointed boards of the good jointed board graph into a virtual bad jointed board
list; and based on the virtual bad jointed board
list, analyzing and comparing the manufacturing process flow data of the virtual bad jointed board and the original defective jointed board, and determining the potential
root cause causing the defect. According to the method, the problems that in the E-
test scene of the circuit board, the number of defect samples is extremely small, categories are extremely unbalanced, an experience threshold value is difficult to set, and root causes are difficult to trace can be solved.