Method for manufacturing grid structure of semiconductor device

Abstract

The invention provides a mehtod for making grid structure of semiconductor device, which includes providing a semiconductor substrate, and forming a grid medium layer on the substrate, and forming a grid electrode layer on the grid medium layer, and forming a mask layer on the grid electrode layer, and then inducing etching gas to etch the polysilicon grid electrode layer by employing plasma output by a plasma source, wherein the plasma source etches the grid medium layer in pulse outputting power manner. The invention provide method for making grid structure of semiconductor device is very effective for accuracy controlling the thickness of the grid oxide layer in a process node no more then 65 nm, and the etching depth can perfectly stop at the surface of the grid oxide layer without hurting the surface of an active region.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor integrated circuits, in particular to a method for manufacturing a gate structure of a complementary metal oxide semiconductor device. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, semiconductor wafers are developing towards higher component density and high integration. The gate of CMOS devices The poles are getting thinner and shorter than ever. In order to avoid the short channel effect and obtain the maximum drain current, the thickness of the gate oxide layer is usually made thinner and thinner. Using a thinner gate oxide layer can enhance the coupling between the gate electrode and channel carriers, making the characteristics of the transistor closer to that of a long-channel device. Since drain curre...

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Problems solved by technology

[0005] Therefore, the object of the present invention is to provide a method for manufacturing the gate structure of a semiconductor device. When etching the gate oxide layer, the plasma source adopts a pulsed output power mode to etch the gate oxide layer to solve the existing problems. The problem that the plasma penetrates the gate oxide layer and recesses the active area and LDD area below it in the technology

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