LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor, semiconductor device and manufacture method thereof

Abstract

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor, a semiconductor device and a manufacture method thereof, wherein the manufacture method of the LDMOS transistor comprises the steps of: forming a deep-doped well in a semiconductor substrate; forming an isolation structure in the deep-doped well, wherein the isolation structure is arranged between a source electrode and a drain electrode and is close to the drain electrode; forming a first ion doping area in the deep-doped well; and forming a second ion doping area in the deep-doped well, wherein a space is reserved between the first ion doping area and the second ion doping area. By forming the deep-doped well which has the same channel conduction type with the LDMOS transistor to be formed in the semiconductor substrate, the invention can obtain higher breakdown voltage.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to LDMOS transistors, semiconductor devices with LDMOS transistors and manufacturing methods thereof. Background technique [0002] In the development of power integrated circuits, the single-chip process developed to integrate power switches and control circuits, especially the lateral double diffusion MOS (lateral double diffusion MOS, LDMOS) process is a mainstream trend. The LDMOS process is planar diffusion on the surface of the semiconductor substrate to form the main lateral current path. Since LDMOS is manufactured in a typical IC process, the control circuit and LDMOS can be integrated on a monolithic power IC. LDMOS The process uses reduced surface electric field (RESURE) technology and low-thickness epitaxy (EPI) or N-type well region (N-well), which can achieve the goals of high voltage and low on-resistance. [0003] The LDMOS device is a field-effect transisto...

AI Technical Summary

Problems solved by technology

[0007] In this technical solution, the P-region 204 is used as the drift region of the drain 209, and the effective channel length is figure 2 As shown in DLL, under the gate voltage, a reverse-biased diode is formed between the P-region 204 and the P-region 204, the depletion region is narrow, and the withstand voltage of the LDMOS transistor is low, resulting in the I-V of the LDMOS transistor A snapback phenomenon will appear quickly in the characteristic curve; moreover, in the process of forming the P-region 204, if the mask deviates, such as the P-region 204 does not completely surround the shallow trench isolation structure 202, it is easy to cause a threshold voltage It is too high to affect the actual use; at the same time, the formation of the P-region 204 requires separate implantation and a separate mask, and the cost is relatively high

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