Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof

A chip package and grid array technology, which is applied in the manufacture of semiconductor devices, electric solid devices, semiconductor/solid devices, etc., can solve the problems of high material cost, low pass rate, and complex frame layout structure design, and achieve heat dissipation effect Good, the design and manufacturing cycle is short, and the effect of speeding up the trial production process

Active Publication Date: 2011-05-25
华天科技(南京)有限公司
View PDF5 Cites 19 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In order to overcome the above-mentioned existing PGA (pin grid array) technology existing in the frame layout structure design is relatively complex, the qualified rate is low, resulting in high material costs, the present invention provides a complex layout design, using copper Lead frame (L / F) has high yield rate, low material cost, and a flat, non-carrier, lead-free grid display IC chip package with short manufacturing cycle. Another object of the present invention is to provide a kind of above-mentioned IC chip Method of making the package

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof
  • Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof
  • Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0131] single chip package

[0132] 1. Thinning and scribing

[0133] Thin the wafer to 150μm first, clean it and dry it, stick the adhesive film on the back, and remove the thinning film. Then the wafer with the adhesive film attached is cut into individual chips, only the adhesive film layer is scratched, and the protective layer is not scratched.

[0134] 2. Core loading

[0135] NLGA9L special frame and adhesive film are adopted. On the dedicated core loading machine, the lead frame is automatically transferred to the core loading machine track, and the chip is automatically placed on the B1, B2 inner pins and B3, A1, A2, A3, C1, C2, C3 The remaining few inner pin edges. That is, for a typical three-row pin, since the NLGA frame has no carrier, the chip with the adhesive film is glued to the B-row double pin (such as NLGA9L, B1, B2, B3) and the remaining pins (such as NLGA9L, A1 , A2, A3, C1, C2, C3), the edges are baked to achieve a firm paste.

[0136] 3. Pressure w...

Embodiment 2

[0158] Dual Die Stacked Package

[0159] The thinning, scribing, printing, and cutting of multi-chip stacked packages are the same as those of single-chip packages, and the matrix gold-plated contacts do not need electroplating.

[0160] 1. Thinning and scribing

[0161] First, the lower wafer is thinned to 200 μm, and the upper wafer is thinned to 100 μm. After cleaning and drying, the adhesive film is pasted on the back and the thinned adhesive film is removed. Then cut the wafer with the adhesive film into individual chips, adjust the scribing depth parameter according to the thickness of the thinned wafer + the film thickness of the adhesive film, and only scratch through the adhesive film layer without scratching the protective layer.

[0162] 2. Core loading

[0163] On the dedicated core loading machine for film sheets, the chip is automatically placed on the corresponding L / F inner pin setting position. After heating, the IC chip 6 is glued to the inner pins of the m...

Embodiment 3

[0186] Multi-chip package

[0187] Thinning, scribing, printing, and cutting of multi-chip packaging are the same as single-chip packaging, and the matrix lead frame uses gold-plated contacts without electroplating.

[0188] 1. Thinning and scribing

[0189] Same as Example 1

[0190] 2. Core loading

[0191] On the dedicated core loading machine for film sheets, the chip is automatically placed on the corresponding L / F inner pin setting position. After heating, the IC chip 6 is glued to the inner pins of the middle row and the edges of the remaining inner pins. For a typical four-row pin, since the NLGA frame has no carrier, the IC chip 6 with the adhesive film is glued to the B row and C row pins (such as NLGA16L: B2, B3 and C2, C3), and the adhesive film The IC chip 9 is glued to the edge of the B4 and C4 pins.

[0192] 3. Pressure welding

[0193] Since the IC chip 6 is glued to the inner pins, the pads on the IC chip are relatively close to the solder joints of the i...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to a carrier-free grid-array IC (Integrated Circuit) chip packaging part and a preparation method thereof. The carrier-free grid-array IC chip packaging part comprises inner pins, IC chips, soldering pads, bonding lines and plastic-sealed bodies, wherein the inner pins are arranged into a multi-row matrix type on the front surface of the packaging part, and multiple rows of exposed round gold-plated contacts approximately to squares are arranged on the back surface of the packaging part; the IC chips are positioned on the upper surfaces of the inner pins, the inner pins and the IC chips are bonded through glue membranes, the soldering pads on the IC chips are connected with the inner pins through the bonding lines, and the glue membranes, the IC chips, the bonding lines and the edges of the inner pins are surrounded by the plastic-sealed bodies to form an integrated circuit. In the invention, since spherical array contacts approximately to squares are adopted, the structure is simple and flexible, and the radiating effect is good. The finished-product rate of a copper lead frame (L / F) is high, and the material cost is lowered. Since the copper lead frame (L / F) is adopted for replacing a ceramic baseplate, a PCB (Printed Circuit Board) baseplate or a BT (Bismaleimide Triazine) baseplate, the complicated layout design is saved, the designing and manufacturing cycle is shorter, the pilot production process is quickened, products are promoted to be on the market in advance, and the first market opportunity is obtained.

Description

technical field [0001] The invention belongs to the technical field of electronic information automation component manufacturing, and relates to an IC chip package, in particular to a carrierless lead-free grid array IC chip package, and also relates to a preparation method of the package. Background technique [0002] The LGA (Land Grid Array) package is a grid array package, a fine-pitch chip-scale package based on a laminated substrate. LGA replaces the past PGA (Pin Grid Array, pin grid array) with metal contact packaging technology, which is a leaping technological revolution. PGA (Pin Grid Array) packaging technology generally uses ceramic substrates, PCB substrates or BT substrates (the logical relationship is not clear), and the layout structure design is relatively complicated, the cost of materials using ceramic substrates, PCB substrates or BT substrates is high, and the substrate production is qualified The efficiency is low, the manufacturing cycle is long, and...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L23/488H01L21/60
CPCH01L24/85H01L2224/73265H01L2223/54486H01L2224/97H01L2224/48137H01L2924/15747H01L2224/48091H01L2224/48145H01L24/05H01L24/48H01L2224/92247H01L23/49575H01L24/97H01L2224/32245H01L23/49541H01L2224/85444H01L2224/2919H01L24/73H01L23/4951H01L2224/32145H01L23/3107H01L24/03H01L2224/49171H01L2224/04042H01L23/49548H01L24/49H01L2224/48247H01L24/92H01L24/32H01L2924/15787H01L2924/181H01L2924/12042H01L2924/14H01L2224/05554H01L2924/00014H01L2924/18301H01L2924/00012H01L2224/83H01L2224/85H01L2924/00H01L2224/45099H01L2224/45015H01L2924/207
Inventor 郭小伟何文海慕蔚王新军
Owner 华天科技(南京)有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap