Carrier-free pin-free grid-array IC (Integrated Circuit) chip packaging part and production method thereof

A chip package and grid array technology, which is applied in the manufacture of semiconductor devices, electric solid devices, semiconductor/solid devices, etc., can solve the problems of high material cost, low pass rate, and complex frame layout structure design, and achieve heat dissipation effect Good, the design and manufacturing cycle is short, and the effect of speeding up the trial production process
CN102074541AActive Publication Date: 2011-05-25华天科技(南京)有限公司

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
华天科技(南京)有限公司
Publication Date
2011-05-25

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention relates to a carrier-free grid-array IC (Integrated Circuit) chip packaging part and a preparation method thereof. The carrier-free grid-array IC chip packaging part comprises inner pins, IC chips, soldering pads, bonding lines and plastic-sealed bodies, wherein the inner pins are arranged into a multi-row matrix type on the front surface of the packaging part, and multiple rows of exposed round gold-plated contacts approximately to squares are arranged on the back surface of the packaging part; the IC chips are positioned on the upper surfaces of the inner pins, the inner pins and the IC chips are bonded through glue membranes, the soldering pads on the IC chips are connected with the inner pins through the bonding lines, and the glue membranes, the IC chips, the bonding lines and the edges of the inner pins are surrounded by the plastic-sealed bodies to form an integrated circuit. In the invention, since spherical array contacts approximately to squares are adopted, the structure is simple and flexible, and the radiating effect is good. The finished-product rate of a copper lead frame (L / F) is high, and the material cost is lowered. Since the copper lead frame (L / F) is adopted for replacing a ceramic baseplate, a PCB (Printed Circuit Board) baseplate or a BT (Bismaleimide Triazine) baseplate, the complicated layout design is saved, the designing and manufacturing cycle is shorter, the pilot production process is quickened, products are promoted to be on the market in advance, and the first market opportunity is obtained.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention belongs to the technical field of electronic information automation component manufacturing, and relates to an IC chip package, in particular to a carrierless lead-free grid array IC chip package, and also relates to a preparation method of the package. Background technique

[0002] The LGA (Land Grid Array) package is a grid array package, a fine-pitch chip-scale package based on a laminated substrate. LGA replaces the past PGA (Pin Grid Array, pin grid array) with metal contact packaging technology, which is a leaping technological revolution. PGA (Pin Grid Array) packaging technology generally uses ceramic substrates, PCB substrates or BT substrates (the logical relationship is not clear), and the layout structure design is relatively complicated, the cost of materials using ceramic substrates, PCB substrates or BT substrates is high, and the substrate production is qualified The efficiency is low, the manufacturing cycle is long, and...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More