Method for preparing metal-oxide-semiconductor field effect transistors (MOSFETs) with extremely short-gate length bulk-silicon surrounding gates

Abstract

The invention discloses a method for preparing metal-oxide-semiconductor field effect transistors (MOSFETs) with extremely short-gate length bulk-silicon surrounding gates, which comprises the following steps of: performing local oxidation of silicon isolation or trench isolation, depositing three layers of medium films which are a cushioning SiO2 oxide layer, SiN and an oxide medium layer respectively on bulk silicon, performing electron beam exposure, etching a groove and fin, depositing SiN sidewalls, isotropically etching Si, performing dry-oxygen oxidation, performing etching to remove the sidewalls on the two sides of the fin and simultaneously reserve the bottom sidewall of the groove, performing three steps of sacrificial oxidation to form nanowires, performing wet etching to reserve sufficiently thick bottom SiO2 for isolation at the same time of releasing the nanowires, depositing a gate medium and a gate material, performing two steps of source-drain injection after the gate is back-etched, depositing and etching the sidewalls, and forming contact. The method eliminates a self-heating effect and a floating body effect, is lower in cost, well compatible with a complementary metal oxide semiconductor process by completely adopting a conventional top-down process, and favorable for inhibiting a short channel effect and promoting the development of MOSFETs with smaller sizes, and easily realizes integration.

Description

technical field [0001] The invention belongs to the technical field of microelectronic nanoscale complementary metal oxide semiconductor devices (CMOS) and extremely large-scale integration, in particular to a method for preparing metal semiconductor field-effect transistors (MOSFETs) with extremely short gate length silicon-surrounded gates . Background technique [0002] Nano-CMOS devices continue to develop in accordance with Moore's law, and the continuous reduction of the size of planar bulk silicon devices has encountered severe challenges. Various new structure devices have emerged, and the gate structure of the device has evolved from the initial single gate to double gate and triple gate. From the surrounding gate structure that completely surrounds the channel, the gate control ability and the ability to suppress the short channel effect are continuously enhanced with the increase in the number of gates. The nanowire-enclosed gate MOSFET with surrounding channel s...

AI Technical Summary

Problems solved by technology

[0008] The main difficulty in fabricating gate-enclosed devices on bulk silicon lies in the formation of sacrificial layers. So far, there are only a few reported fabrication methods using bulk silicon substrates or damascene dummy gate processes that require complex and expensive epitaxial SiGe as a sacrificial layer. Or directly isotropically etch Si to cause contamination of the substrate, and inevitably cause large parasitic capacitance resistance, these have obvious shortcomings and limitations for further size reduction

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