High-speed low-noise semiconductor device structure and method for forming same

Abstract

The invention provides a high-speed low-noise semiconductor device structure and a method for forming the same. The structure comprises a substrate, a relaxation silicon germanium (SiGe) transition layer and a high-Ge component strain layer, wherein the relaxation SiGe transition layer is formed on the substrate; the high-Ge component strain layer is formed on the relaxation SiGe transition layer; the high-Ge component strain layer is provided with a groove, a strain silicon-carbon (Si-C) alloy cap layer, a T-type gate structure and source and drain electrodes; the strain Si-C alloy cap layer is formed on the high-Ge component strain layer; the T-type gate structure is formed on a part of the strain Si-C alloy cap layer and covers the groove; and the source and drain electrodes are formed on two sides of the T-type gate structure. In structures of a P-channel metal oxide semiconductor (PMOS) device and an N-channel metal oxide semiconductor (NMOS) device provided by the embodiment of the invention, a hole potential well can be generated in a high-Ge component strain SiGe layer or a high-Ge component strain Ge layer by arranging two low-Ge component strain SiGe layers or strain Si-C alloy layers above and below the high-Ge component strain SiGe layer or the high-Ge component strain Ge layer, so that hole mobility and electron mobility can be improved, and the performance of the device is improved greatly.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing and design, in particular to a high-speed and low-noise semiconductor device structure and a forming method thereof. Background technique [0002] For a long time, the feature size of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been following the so-called Moore's law (Moore's law), and its working speed is getting faster and faster. However, for Si-based material itself As far as it is concerned, it is already close to the double limit of physics and technology. Therefore, various methods have been proposed in order to continuously improve the performance of MOSFET devices, and thus the development of MOSFET devices has entered a so-called post-Moore (More-Than-Moore) era. High-mobility channel engineering based on heterojunction structures, especially material systems such as Si-Ge and Si-C, is one of the effective technologies. The core idea of ​​this te...

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Problems solved by technology

On the other hand, the hole mobility of bulk silicon is only about half of the electron mobility. In order to obtain the same driving capability, the channel width of the PMOSFET device is about twice that of the NMOSFET, which not only wastes the layout area, but also outputs parasitic The increase of capacitance also reduces the working speed of the circuit, so how to significantly improve the hole mobility of PMOS devices is particularly prominent

[0003] Furthermore, since the minimum noise factor of MOSFET devices is proportional to the gate resistance and source region resistance, in order to obtain high-speed, low-noise MOSFET devices, it is first required to reduce the gate length while maintaining or reducing the source and drain region resistance , and the reduction of the gate length will inevitably lead to the increase of the gate resistance, which will increase the noise figure of the device

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