Multilayer copper interconnection manufacturing method

Abstract

The invention relates to a copper interconnection manufacturing method belonging to the field of micro-nano manufacture. The method utilizes the sputtering or atomic layer deposition technology to prepare a copper nitride film, and utilizes a femtosecond laser writing technology to form copper elementary substance at the area needing metal interconnection by using laser decomposition, thus realizing copper interconnection by one step; and since the metal copper is formed by conducting laser thermal decomposition on the plane of the copper nitride, additional chemical polishing is not needed to realize surface planarization.

Description

technical field [0001] The invention relates to a copper interconnection manufacturing method, which belongs to the field of micro-nano manufacturing. Background technique [0002] In the field of microelectronics, as the feature size of integrated circuit devices continues to shrink, in order to improve the reliability and service life of devices, the metal interconnection of chips is transferred from aluminum interconnection to copper interconnection. Multilayer interconnection technology has become VLSI and ultra-large-scale An important part of the integrated circuit (ULSI) manufacturing process; multi-layer interconnection structure, mainly including local interconnection, metal interconnection and interconnection between upper and lower metal lines, etc., and insulating medium is required between metal interconnections For isolation, the insulating layer is called interlayer dielectric (ILD), and it is also the physical support of the upper metal line. The requirement ...

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Problems solved by technology

[0003] Since the chloride produced by copper metal in the etching process is not volatile, it is impossible to use plasma etching to prepare graphics. The Dual Damascene (Dual Damascene) process invented by IBM solves this problem ingeniously. In the dual Damascene process, Firstly, the oxide dielectric layer is etched to generate a trench for the damascene process, followed by deposition of a metal barrier layer and a copper seed layer, and then the trench is filled with copper through the ECP electroplating process, and finally, Cu chemical mechanical polishing ( CMP) process to achieve copper planarization. Copper interconnect chemical mechanical polishing is currently the only practical technology and core technology that can achieve global planarization of chips. This technology has many processes and complex processes.

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