Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

N-channel accumulative SiC IEMOSFET (Implantation and Epitaxial Metal-Oxide-Semiconductor Field Effect Transistor) device and manufacturing method thereof

An accumulation type and channel technology, applied in the field of microelectronics, can solve the problems of reduced electron mobility in the inversion layer, increased device on-resistance, and affecting device performance, achieving increased mobility, reduced on-resistance, The effect of simple process

Active Publication Date: 2013-03-20
陕西半导体先导技术中心有限公司
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Although the use of this structure and process improves the interface characteristics of the device to a certain extent, because the buried channel 6 of the device is still formed by ion implantation, the resulting SiC and SiO 2 A series of problems such as rough contact interface, high lattice damage, and low activation rate make the electron mobility of the inversion layer greatly reduced and the on-resistance of the device increase, which seriously affects the performance of the device.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • N-channel accumulative SiC IEMOSFET (Implantation and Epitaxial Metal-Oxide-Semiconductor Field Effect Transistor) device and manufacturing method thereof
  • N-channel accumulative SiC IEMOSFET (Implantation and Epitaxial Metal-Oxide-Semiconductor Field Effect Transistor) device and manufacturing method thereof
  • N-channel accumulative SiC IEMOSFET (Implantation and Epitaxial Metal-Oxide-Semiconductor Field Effect Transistor) device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0038] Step 1. In N + Epitaxial growth of N on SiC substrate - Drift layer.

[0039] to N + The silicon carbide substrate 11 was cleaned by RCA cleaning standard, and then epitaxially grown on the surface of the substrate with a thickness of 8 μm and a nitrogen ion doping concentration of 1×10 15 cm -3 N - Drift layer 10, such as image 3 a. The process conditions are as follows: the epitaxy temperature is 1570°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

[0040] Step 2. Multiple times of selective implantation of aluminum ions to form a P well.

[0041] (2.1) Deposit a layer of SiO with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition 2 layer, and then deposit Al with a thickness of 1 μm as a barrier layer for the ion implantation of the P well 9, and form the P well implantation region by photolith...

Embodiment 2

[0068] Step 1. In N + Epitaxial growth of N on SiC substrate - Drift layer.

[0069] to N + The silicon carbide substrate 11 was cleaned by RCA cleaning standard, and then epitaxially grown on the surface of the substrate with a thickness of 8.5 μm and a nitrogen ion doping concentration of 1.5×10 15 cm -3 N - Drift layer 10, such as image 3 a. The process conditions are as follows: the epitaxy temperature is 1570°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

[0070] Step 2. Multiple times of selective implantation of aluminum ions to form a P well.

[0071] (2.1) Deposit a layer of SiO with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition 2 layer, and then deposit Al with a thickness of 1 μm as a barrier layer for the ion implantation of the P well 9, and form the P well implantation region by photo...

Embodiment 3

[0098] Step A. In N + Epitaxial growth of N on SiC substrate - Drift layer.

[0099] to N + The silicon carbide substrate 11 is cleaned by RCA cleaning standard, and then epitaxially grown on the surface of the substrate with a thickness of 9 μm and a nitrogen ion doping concentration of 2×10 15 cm -3 N - Drift layer 10, such as image 3 a. The process conditions are as follows: the epitaxy temperature is 1570°C, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen.

[0100] Step B. multiple times of selective implantation of aluminum ions to form a P well.

[0101] (B1) Deposit a layer of SiO with a thickness of 0.2 μm on the front side of the silicon carbide wafer by low-pressure hot-wall chemical vapor deposition 2 layer, and then deposit Al with a thickness of 1 μm as a barrier layer for the ion implantation of the P well 9, and form the P well implantation region by photolithog...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an N-channel accumulative SiC IEMOSFET (Implantation and Epitaxial Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof, which are mainly used for solving the problems of low channel electron mobility and large conductor resistance of the SiC IEMOSFET device in the prior art. The device is technically characterized in that: on the basis of the conventional SiC IEMOSFET device structure, a conducting channel layer formed by injecting is replaced by an N-epitaxial accumulation layer (6') of which the thickness is between 0.1 mum and 0.2 mum and the nitrogen ion dosage concentration is 4*10<16>cm<-3>; and the epitaxial accumulation layer (6') is transversely positioned between a left source region N<+> contact (4a) and a right source region N<+> contact (4b) and is longitudinally positioned between a separation medium (2) and a JFET (Junction Field Effect Transistor) area (8). The device has the advantages of high channel electron mobility, low on resistance and low energy consumption, and can be applied to the fields such as automobile electrons, computers, communications and the like.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and relates to a semiconductor device, in particular to an N-channel accumulation type SiC IEMOSFET device and a preparation method. Background technique [0002] SiC has become one of the most advantageous semiconductor materials for manufacturing high-temperature, high-power electronic devices due to its excellent physical, chemical and electrical properties, and has a power device quality factor much greater than that of Si materials. The research and development of SiC power device MOSFET began in the 1990s. It has a series of advantages such as high input impedance, fast switching speed, high operating frequency, and high temperature and high pressure resistance. It has been used in switching regulated power supplies, high-frequency heating, automotive electronics and power amplifiers. and so on have been widely used. [0003] However, the current SiC power MOS devices SiC and SiO ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336H01L21/20H01L21/265
Inventor 汤晓燕张超张玉明张义门杨飞王文
Owner 陕西半导体先导技术中心有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com