Capacitance-free dynamic random access memory structure and preparation method thereof

Abstract

The invention discloses a capacitance-free dynamic random access memory structure and a preparation method thereof. Under the premise that the capacitance-free dynamic random access memory structure meets high voltage leakage requirements for a high impact ionization rate, the electrical thickness of a gate medium in a source drain junction area is increased via adoption of different gate medium materials or gate medium thicknesses near the area, an electric field in the vertical direction is reduced effectively. Meanwhile, a thin oxidation layer or a high K material is adopted in the central area of a channel, the gate control capability is improved, and the short channel effect is inhibited. By adopting the structure, the degradation of the gate medium can be inhibited effectively, the reliability (durability) of a storage unit can be improved, the scaling-down of a device can be facilitated, and the complex process for the capacitance structure in the conventional 1T1C structure can be avoided completely in the capacitance-free structure. The adopted manufacturing process is completely compatible with the conventional logic process, and the high-density three-dimensional process integration can also be facilitated.

Description

technical field [0001] The invention relates to the technical fields of microelectronics manufacturing and memory, in particular to a highly reliable non-capacitive dynamic random access memory structure and a preparation method thereof. Background technique [0002] Microelectronics products are mainly divided into two categories: logic devices and memory devices. As an important part of storage devices, dynamic random access memory (DRAM) can provide high-speed data read and write operations, but the stored information is easily lost in the event of power failure, so it is called volatile semiconductor memory. In computer systems, DRAMs are generally placed between high-speed microprocessors and low-speed non-volatile memories, and are used to match high-speed data processing and low-speed data access. With the continuous development of information technology, the development of high-speed and high-density DRAM has become an important direction of storage technology resea...

AI Technical Summary

Problems solved by technology

In this programming mode, the drain terminal voltage is greater than the gate voltage due to the high impact ionization rate, such as Vg=0.5V, Vd=2V, Vs=0V, so the generated holes are still moving to the substrate. Part of it moves to the gate dielectric, thereby generating interface traps and oxide layer traps near the drain junction. With multiple programming and erasing operations, the holes in the gate dielectric will further accumulate, resulting in the threshold voltage of the channel near the drain region Reduced, thus causing information disturbance or error when data is read

For programming mode with tunneling BTBT ( figure 2 b), usually the source terminal is floating, and the drain terminal voltage is much higher than the gate voltage, such as Vg=0V, Vd=4V. In this mode, electrons will move to the drain through band-band tunneling, and the generated holes will flow to the substrate When the bottom moves, due to the large potential difference between the gate and the drain, some will enter the gate near the drain junction, which will also cause the degradation of the gate dielectric and cause data disturbance or read errors.

Although lowering the drain terminal voltage can partially suppress the degradation of the gate dielectric layer, while the low drain terminal voltage significantly reduces the probability of impact ionization and is not conducive to the generation of holes, the probability of electrons generated by impact ionization entering the gate dielectric will rapidly increase. rise, it will also cause reliability problems of the device, so using low drain voltage is not an effective means

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