On-chip network router based on field programmable gate array (FPGA)

Abstract

The invention discloses an on-chip network router based on a field programmable gate array (FPGA). Multiple routers are connected together through internet protocol (IP) multiplex to form a communication network. Each router mainly consists of an exchange switcher and port link modules in the n+1 directions, wherein the n represents the number of existing adjacent routers, and the port link module in each direction comprises an input virtual channel caching module, a virtual channel controller, a router decoder and a request arbiter. The on-chip network router based on the FPGA has the advantages of being simple in structure, low in resource using rate, low in power consumption and reusable, can form the communication network through the IP multiplex technology and is applied in an on-chip network system.

Description

technical field [0001] The invention relates to the technical field of on-chip multi-processor inter-core communication, in particular to an FPGA-based on-chip network router. Background technique [0002] System-on-a-chip is a relatively mature integrated circuit design method at present. Its design idea is to start from the whole of the system and complete the functions of the entire system on a single chip. With the continuous advancement of semiconductor process technology, chips are also rapidly developing in the direction of miniaturization and complexity. The further increase of the scale of the system on a chip makes the number of IP cores integrated on a single chip more and more, which requires higher bandwidth to meet the requirements of the system. However, the reduction of metal line width and spacing not only increases the parasitic resistance on the line, but also increases the coupling capacitance between lines, which severely limits the bus bandwidth and in...

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Problems solved by technology

However, the reduction of metal line width and spacing not only increases the parasitic resistance on the line, but also increases the coupling capacitance between lines, which severely limits the bus bandwidth and increases power consumption sharply.

During the design process of the system-on-chip, problems such as difficulty in meeting the requirements of the communication capability and difficulty in synchronizing the global clock have been encountered, which restrict the scale and quantity of IP cores integrated on a single chip

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