Preparation method for low excursion flat belt voltage silicon carbide (SiC) metal oxide semiconductor (MOS) capacitance

A technology of flat-band voltage and manufacturing method, which is applied in the field of microelectronics, can solve problems such as difficult nitrogen-containing gas dosage, influence on device interface characteristics, flat-band voltage offset, etc., and achieve reduction of dangling bonds, ease of interface stress, and flat-band voltage The effect of small offset

Inactive Publication Date: 2012-12-26
XIDIAN UNIV
View PDF5 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this process has improved the interface characteristics of SiC MOS capacitor devices to a certain extent, there are still large flat-band vol

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Preparation method for low excursion flat belt voltage silicon carbide (SiC) metal oxide semiconductor (MOS) capacitance

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0019] Embodiment 1, including the following steps:

[0020] Step 1. Perform standard cleaning treatment on the N-SiC epitaxial material:

[0021] 1.1) Ultrasonic cleaning of N-SiC epitaxial material with deionized water;

[0022] 1.2) Clean with concentrated sulfuric acid, heat it to smoke and cook for 10 minutes, soak for 30 minutes, and rinse the surface with deionized water several times;

[0023] 1.3) Use H with a ratio of 5:1:1 2 O, H 2 O 2 Soak the N-SiC epitaxial material in a water bath with deionized water for 5 minutes at a temperature of 80℃, and then wash with hydrogen fluoride solution, and rinse the surface several times with deionized water for the second time. ;

[0024] 1.4) Use H with a ratio of 6:1:1 2 O, H 2 O 2 Soak the N-SiC epitaxial material in a water bath after the second rinse with deionized water for 5 minutes with the No. 2 mixed liquid composed of HCl and HCl at a temperature of 80°C, and clean with hydrogen fluoride solution, and then use deionized water...

Example Embodiment

[0029] Embodiment 2, including the following steps:

[0030] Step 1. Perform standard cleaning treatment on the N-SiC epitaxial material:

[0031] 1.1) Ultrasonic cleaning of N-SiC epitaxial material with deionized water;

[0032] 1.2) Clean with concentrated sulfuric acid, heat it to smoke and cook for 10 minutes, soak for 30 minutes, and rinse the surface with deionized water several times;

[0033] 1.3) Use H with a ratio of 5:1:1 2 O, H 2 O 2 Soak the N-SiC epitaxial material in a water bath with deionized water for 5 minutes at a temperature of 80℃, and then wash with hydrogen fluoride solution, and rinse the surface several times with deionized water for the second time. ;

[0034] 1.4) Use H with a ratio of 6:1:1 2 O, H 2 O 2 Soak the N-SiC epitaxial material in a water bath after the second rinse with deionized water for 5 minutes with the No. 2 mixed liquid composed of HCl and HCl at a temperature of 80°C, and clean with hydrogen fluoride solution, and then use deionized water...

Example Embodiment

[0039] Embodiment 3 includes the following steps:

[0040] Step 1. Perform standard cleaning treatment on the N-SiC epitaxial material:

[0041] 1.1) Ultrasonic cleaning of N-SiC epitaxial material with deionized water;

[0042] 1.2) Clean with concentrated sulfuric acid, heat it to smoke and cook for 10 minutes, soak for 30 minutes, and rinse the surface with deionized water several times;

[0043] 1.3) Use H with a ratio of 5:1:1 2 O, H 2 O 2 Soak the N-SiC epitaxial material in a water bath with deionized water for 5 minutes at a temperature of 80℃, and then wash with hydrogen fluoride solution, and rinse the surface several times with deionized water for the second time. ;

[0044] 1.4) Use H with a ratio of 6:1:1 2 O, H 2 O 2 Soak the N-SiC epitaxial material in a water bath after the second rinse with deionized water for 5 minutes with the No. 2 mixed liquid composed of HCl and HCl at a temperature of 80°C, and clean with hydrogen fluoride solution, and then use deionized water f...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Diameteraaaaaaaaaa
Diameteraaaaaaaaaa
Login to view more

Abstract

The invention discloses a manufacturing method for a low excursion flat belt voltage silicon carbide (SiC) metal oxide semiconductor (MOS) capacitance, mainly solving the problem of higher trap density of an silicon dioxide (SiO2)/SiC interface. The manufacturing process of the low excursion flat belt voltage SiC MOS capacitance is as follows: standardly cleaning nitrogen silicon-carbide (N-SiC) epitaxial material; depositing a layer of aluminum nitride (AlN) with the thickness in a range of 1-10nm on the cleaned N-SiC epitaxial material with a molecular beam epitaxy method; dry-oxygen oxidizing a layer of SiO2 with the thickness in a range of 10-100nm on the N-SiC epitaxial material processed by the epitaxy AlN; finishing annealing and cooling in turn to the oxidized N-SiC epitaxial material in argon environment; manufacturing an electrode on the cooled N-SiC epitaxial material through vacuum sputtering aluminum, and secondarily annealing in the argon environment to finish manufacturing the whole SiC MOS capacitance. The low excursion flat belt voltage SiC MOS capacitance has the advantages of low in trap density of the SiO2/SiC interface, small in MOS capacitance flat belt voltage excursion and simple in technology, thereby being used for improving SiO2/SiC interfacial characterization of SiC MOS capacitance.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and relates to the manufacture of semiconductor devices, in particular to a method for manufacturing SiC MOS capacitors. Background technique [0002] Silicon carbide is a wide bandgap semiconductor material that has developed rapidly in the past ten years. It is the only wide-bandgap semiconductor that can generate SiO through natural oxidation 2 Compared with other semiconductor materials, such as Si and GaAs, silicon carbide materials have the advantages of wide bandgap, high thermal conductivity, high carrier saturation mobility, and high power density. Therefore, research on SiC devices and processes has become a hot spot in the field of semiconductor devices. SiC devices usually work under high-voltage and high-power conditions, which require better quality of the oxide layer, relatively small channel resistance, and relatively high effective mobility. These problems have been hi...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H01L21/02
Inventor 汤晓燕多亚军张玉明吕红亮宋庆文
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap