Formation method of groove-shaped semiconductor structure

Abstract

The invention discloses a formation method of a groove-shaped semiconductor structure. Due to the fact that polycrystalline silicon or amorphous silicon is mixed with carbide (C) to fill a groove, or polycrystalline silicon carbide (Si C) or amorphous Si C replaces the polycrystalline silicon or the amorphous silicon to fill the groove, stress of a component is capable of being reduced, and thereby defects inside silicon caused by the stress of the polycrystalline silicon or the amorphous silicon are prevented, and therefore the trench gate semiconductor structure with low stress and defect concentration or a groove access with low resistance is obtained.

Description

technical field [0001] The invention belongs to a semiconductor process method in a semiconductor integrated circuit, in particular to a method for forming a trench-shaped semiconductor structure. Background technique [0002] Polycrystalline or amorphous silicon trench structures are widely used in various semiconductor devices, such as trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, gold oxide half field effect transistor) and IGBT (Insulated Gate Bipolar Transistor, insulation gate bipolar transistors), low-resistance vertical conduction paths in radio frequency semiconductor devices, etc. Polycrystalline or amorphous silicon trenches are generally placed in single crystal silicon. Due to the difference in crystal structure, the thermal expansion coefficients of polycrystalline or amorphous silicon and single crystal silicon are quite different, and the thermal expansion coefficient of single crystal silicon is around 3.0. , while the thermal expansion ...

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Problems solved by technology

Polycrystalline or amorphous silicon trenches are generally placed in single crystal silicon. Due to the difference in crystal structure, the thermal expansion coefficients of polycrystalline or amorphous silicon and single crystal silicon are quite different. The thermal expansion coefficient of single crystal silicon is about 3.0 , while the thermal expansion coefficient of polycrystalline or amorphous silicon is around 6.0, so devices with polycrystalline or amorphous silicon trench structures tend to generate greater pressure after undergoing subsequent thermal processes, especially for relatively high integration Due to the relatively high density of the trenches, the stress will be more obvious; in addition, the trenches with large and deep trenches will also cause greater stress.

Stress is generally a bad phenomenon in semiconductor manufacturing. Usually, it should be avoided or minimized. If the stress is too large, the silicon wafer will be deformed, which will lead to problems in silicon wafer transmission, and will also lead to difficulties in subsequent processing and uniform process. In addition, too much stress inside the single crystal silicon will lead to defects, such as slip planes and slip lines.

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