A kind of outcropping process on the back of tsv

Abstract

The invention discloses a through silicon via (TSV) back surface exposure process. By retaining a substrate above a TSV during the grinding of the back surface of the substrate, the damage to an exposed part of the TSV and the substrate caused by a physical thinning process is avoided, and the ground surface of the substrate with high total thickness variation (TTV) has high surface smoothness, so that the consistency in the subsequent etching process is high. The substrate is etched by an etching solution with high selection ratio of the substrate to a medium layer through a first wet method, the situation of etching of the medium layer and a barrier layer on the TSV for the first time decides whether or not the substrate is etched for the second time and the third time, the exposed part of the TSV has an enough height, and a conductive column of the exposed part is protected from being damaged by the etching solution. A photosensitive material serves as a medium protection layer, and a final TSV exposure structure is etched in an exposure and development manner, so that the corrosion and oxidization of conductive column copper in the conventional process are avoided, and the subsequent processing steps are simplified.

Description

technical field

[0001] The invention relates to a method for manufacturing or processing semiconductor or solid devices or parts thereof in the technical field of microelectronics, in particular to a TSV outcropping process for transmitting current between separate components in a microelectronic device by using metal 3D interconnection. Background technique

[0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits has been continuously reduced and the interconnection density has been continuously increased. At the same time, users' requirements for high performance and low power consumption continue to increase. In this case, the way to improve the performance by further reducing the line width of the interconnection is limited by the physical characteristics of the material and the equipment process, and the resistance-capacitance (RC) delay of the two-dimensional interconnection gradually becomes the limit to improve ...

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