Small-size MOSFET(metal-oxide semiconductor field effect transistor) structure of self-alignment hole and manufacturing method

Abstract

The invention discloses a manufacturing method of a small-size MOSFET (metal-oxide semiconductor field effect transistor) structure of a self-alignment hole. The manufacturing method includes steps of 1) etching a groove, growing gate-oxide, depositing polycrystalline silicon and re-etching; 2) growing a liner oxidation layer, injecting a body area and a source area and thermally annealing; 3) depositing silicon nitride and LPTEOS; 4) re-etching and removing TEOS and silicon nitride; 5) depositing interlevel dielectric layer and flattening; 6) coating photoresist and exposing the contact hole; removing the photoresist, drily etching the interlevel dielectric layer to the silicon surface, performing silicon etching to form a bottom groove of the contact hole. The invention further discloses an MOSFET structure manufactured by the manufacturing method. On the basis of conventional manufacturing process, deposition and etching of SiN and the LPTEOS are added, self-alignment of the contact hole and a grid groove is realized, and accordingly, on the premise of not increasing the number of photoetching layers, the problem of sleeve accuracy of the contact hole in the process of decreasing cellular size is solved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a structure of a small-sized trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with self-aligned contact holes and a manufacturing method thereof. Background technique [0002] At present, in semiconductor integrated circuits, the cell region structure of ordinary trench power MOS transistors is as follows: figure 1 As shown, the cell structure is composed of trenches and contact holes. The contact holes form ohmic contacts by injecting high-dose dopants to lead out the body region and source region. The contact holes are dry-etched after a photolithographic exposure. The dielectric layer is formed. This structure is generally used in 1.0 μm to 1.8 μm cell size designs. [0003] In order to further increase the channel density and reduce the on-resistance (Ron) of the device, the easiest way is to further reduce the cell size design....

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a small-sized MOSFET manufacturing method with self-aligned contact holes, which can solve the problem of insufficient registration accuracy of the contact holes encountered when the cell size design of the trench MOSFET is reduced

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