Method for manufacturing three-dimensional capacitively coupled interconnection structure based on through-silicon capacitor

Abstract

The invention discloses a method for manufacturing a three-dimensional capacitively coupled interconnection structure based on a through-silicon capacitor. The method comprises: forming two silicon substrates same in structure by machining, and bonding the back surface of one silicon substrate to the other silicon substrate in an alignment manner; forming the three-dimensional capacitively coupled interconnection structure based on the through-silicon capacitor; coaxially arranging copper columns at the upper part and the lower part of the interconnection structure; enabling the top of the copper column at the lower part to be in contact with a silicon dioxide insulation layer on the back surface of the silicon substrate at the upper part; and taking the copper column at the upper part and the copper column at the lower part as an upper electrode plate and a lower electrode plate of the capacitance respectively, taking an insulation layer between the copper column at the upper part and the copper column at the lower part as an inter-capacitance medium, and forming a through-silicon capacitor structure. Compared with a conventional TSV process, the method has the characteristics that the technological processes of making metal convex points on the front surface of a wafer, thinning the back surface to expose copper, performing insulation treatment, making micro-convex points and the like in a TSV structure making process are removed, the technological processes are remarkably reduced, the yield is increased, and required process devices are correspondingly reduced.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to a manufacturing method of a three-dimensional capacitive coupling interconnection structure. Background technique [0002] Currently commonly used three-dimensional integrated interconnection structures mainly include through-silicon vias (TSV: Through Silicon Via) and capacitive / inductive coupling. TSV originated from the US patent "Semiconductive wafer and method of making the same" (3,0044,909) filed by William Shockley in 1958, which used the "deeppits" structure to realize signal transmission from the front to the back. The TSV vertical interconnection structure is based on the structure proposed in the literature "Through Silicon Via Technology–Processes and Reliability for Wafer-Level 3D System Integration" (Ramm, P. and Wolf, M.J published in ECTC58th in 2008) and "Through-Silicon Via (TSV)" (MakotoMotoyoshi published in Proceeding of the IEEE in 2009...

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Problems solved by technology

[0003] The purpose of the present invention is to provide a method for manufacturing a three-dimensional capacitively coupled interconnection structure based on through-silicon capacitors, so as to solve the problem of lower performance and yield after three-dimensional integration of devices caused by the complex manufacturing process of TSV vertical interconnection structures, and the problem of capacitive / inductive coupling vertical The interconnection structure cannot achieve multi-layer chip stacking, and due to the large footprint, it can only be used for three-dimensional coupling and interconnection at the periphery of the chip (such as pads), and cannot be directly used inside the 3D-IC chip to achieve three-dimensional integration like the TSV structure. interconnection problem

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