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Method for fabricating multi-wavelength photonic integrated emission chip by stacked selective growth

A photon integration and selective growth technology, applied in phonon exciters, lasers, laser devices, etc., can solve the problems of different EAM extinction ratios, low device yields, affecting dynamic characteristics, etc., to achieve consistent extinction ratios, optimized performance, The effect of improving performance

Active Publication Date: 2019-03-22
INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] As mentioned above, in order to prepare multi-wavelength photonic integrated emission chips with good performance, most of them require complex processes, resulting in low device yield and high manufacturing costs.
In addition, in the current integrated electroabsorption modulated laser (EML) chip, the EAM material characteristics of each channel are consistent, and the DFB lasing wavelengths corresponding to different channels are different, and the difference between the PL peak wavelength of each channel EAM and the DFB lasing wavelength is uniform. different, which leads to different EAM extinction ratios of different channels, which in turn affects its dynamic characteristics

Method used

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  • Method for fabricating multi-wavelength photonic integrated emission chip by stacked selective growth
  • Method for fabricating multi-wavelength photonic integrated emission chip by stacked selective growth
  • Method for fabricating multi-wavelength photonic integrated emission chip by stacked selective growth

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Embodiment 1

[0028] Please refer to figure 1 and Figure 2 to Figure 11 , the present invention provides a method for fabricating a multi-wavelength photon integrated emission chip by stacked selective growth, and the multi-wavelength photon integrated emission chip includes a detector (PD), a laser (DFB), a modulator (EAM) and an amplifier (SOA). Active devices and passive waveguides, including the following steps:

[0029] Step 1: making a selective area dielectric mask pair 2 in the detector area on the InP substrate 1, the medium in the selected area dielectric mask pair 2 is silicon oxide or silicon nitride, and the thickness of the medium is 50-200 nanometers, The pair of selective dielectric mask strips 2 appear in pairs at the interval of the array unit, the interval of the array unit interval is 100 microns to 300 microns, and the distance between the selective dielectric mask strips 2 corresponding to different array units is 5 microns Gradient to 50 microns, where the schemati...

Embodiment 2

[0044] This embodiment is basically the same as Embodiment 1, except that: first, the laser region grating is a uniform grating, and the different lasing wavelengths of each channel laser are determined by the different ridge widths of the laser region; second, the selective dielectric mask strip The spacing between pairs remains unchanged at 15 microns, and the width of mask strips gradually changes from 5 microns to 50 microns. The schematic diagram of the structure is as follows Figure 13 shown.

[0045] To sum up, the multi-wavelength photonic integrated emission chip can be fabricated by stacking selected area growth method, and the laser quantum well material and the electroabsorption modulator quantum well material can be designed and optimized separately. By adjusting the spacing and width of the dielectric mask strip pair, EML arrays with the same extinction ratio can be obtained by selectively growing stacked quantum wells in the electroabsorption modulator region. ...

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Abstract

Disclosed is a method for manufacturing a multi-wavelength photon-integrated transmitting chip through a lamination and selective-area-growth mode. The method comprises the steps of manufacturing selective-area dielectric mask strip pairs on a substrate; enabling an InP buffer layer, a lower respective limiting layer, a lower multi-quantum-well layer, an etching stop layer, an upper multi-quantum-well layer, and an upper respective limiting layer to be grown in sequence; removing a part of the upper respective limiting layer and the upper multi-quantum-well layer; removing a part of the etching stop layer and the lower multi-quantum-well layer; enabling a passive waveguide core layer to be grown in a butt-jointing manner; manufacturing distributed feedback gratings on the upper respective limiting layer, performing epitaxial growth of a grating coverage layer, a doped cover layer and a heavily-doped contact layer in sequence, and etching off a part of the heavily-doped contact layer; etching active waveguide, passive waveguide and deep waveguide structures; enabling an insulating dielectric layer to be grown; forming an electrode contact window; preparing a metal P electrode; forming an isolation trench; and manufacturing another metal N electrode on the back surface of the substrate to complete the preparation of the chip.

Description

technical field [0001] The invention relates to the field of optoelectronic devices, in particular to a method for manufacturing a multi-wavelength photon integrated emission chip by lamination selective growth. Background technique [0002] The capacity of optical fiber communication systems has grown exponentially with the rapid increase in human demand for information capacity, thus putting high reliability, low cost and low loss photonics integrated circuits technology on the agenda. Monolithic integrated multi-wavelength photonic integrated emission chip is an important means to realize photonic integration, it contains a variety of functional devices: photodetector (PD), distributed feedback laser (DFB), electroabsorption modulator (EAM), semiconductor optical amplifier (SOA), passive waveguide and passive wave combining devices such as multimode interference coupler (MMI), arrayed waveguide grating (AWG), etc., the device preparation process is complex, and the produc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01S5/343H01S5/40
CPCH01S5/34306H01S5/3436H01S5/34366H01S5/4087
Inventor 邓秋芳梁松许俊杰朱洪亮
Owner INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI