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Semiconductor device and preparation method thereof, electronic device

A technology of electronic devices and semiconductors, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., can solve the problems of hole formation, device performance degradation, yield reduction, etc.

Inactive Publication Date: 2017-04-05
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Among them, the method of solid source-drain doping can be used to dope the bottom of the channel, and the upward diffusion to the channel and the damage of ion implantation can be well controlled by the method, but there are other problems in the method, For example, during this process, the coating deposition of BARC will form holes, etc., resulting in a decrease in device performance and yield.

Method used

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  • Semiconductor device and preparation method thereof, electronic device
  • Semiconductor device and preparation method thereof, electronic device
  • Semiconductor device and preparation method thereof, electronic device

Examples

Experimental program
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Embodiment 1

[0045] Combine below Figures 1a-1k as well as figure 2 The semiconductor device and the preparation method of the present invention will be further described.

[0046] Step 101 is performed to provide a semiconductor substrate 101 and perform ion implantation to form wells.

[0047] The semiconductor substrate 101 in this step may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S- SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc.

[0048] The semiconductor substrate 101 includes an NMOS region and a PMOS region, so as to form NMOS devices and PMOS devices in subsequent steps.

[0049] Next, a pad oxide layer (Pad oxide) is formed on the semiconductor substrate 101, wherein the formation method of the pad oxide layer (Pad oxide) can be formed by a deposition method, such as chemical vapor deposition, atomic layer deposition and other methods , c...

Embodiment 2

[0102] A semiconductor substrate 101, the semiconductor substrate includes an NMOS region and a PMOS region;

[0103] Fins 102 located on the NMOS region and the PMOS region;

[0104] an isolation material layer 107 located on the semiconductor substrate and covering part of the fins;

[0105] Wherein, a boron-containing material layer 105 and a cover layer 106 are sequentially formed on the surface of the portion of the fin covered by the isolation material layer 107, and in the PMOS region, the fin and the boron-containing material layer 105 An ion diffusion barrier layer 103 is also formed therebetween.

[0106] Wherein, the semiconductor substrate 101 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI) , silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

[0107] Wherein, the semiconductor substrate 101 includes an NMOS region and a ...

Embodiment 3

[0122] The present invention also provides an electronic device, including the semiconductor device described in the second embodiment. Wherein, the semiconductor device is the semiconductor device described in the second embodiment, or the semiconductor device obtained according to the preparation method described in the first embodiment.

[0123] The electronic device of this embodiment can be any electronic product or equipment such as mobile phone, tablet computer, notebook computer, netbook, game console, TV set, VCD, DVD, navigator, camera, video recorder, voice recorder, MP3, MP4, PSP, etc. , can also be any intermediate product including the semiconductor device. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

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Abstract

The invention relates to a semiconductor device and a preparation method thereof, and an electronic device; the method comprises the following steps: S1, providing a semiconductor substrate having a NMOS zone and a PMOS zone, wherein a plurality of fins are formed on the NMOS zone and the PMOS zone; S2, forming an ion diffusion barrier layer on the fins in the PMOS zone, thus preventing ion diffusion; S3, forming a boron containing material layer and a cover layer on the fins in the NMOS zone and the ion diffusion barrier layer in the PMOS zone; S4, forming an isolation material layer on the semiconductor substrate so as to partially cover the fins, thus forming the fins with a target height; S5, removing the boron containing material layer and the cover layer on the exposed fins, simultaneously removing the ion diffusion barrier layer on the exposed fins in the PMOS zone, thus exposing said fins; S6, executing an annealing step so as to carry out diffusion doping of boron in the boron containing material.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular, the present invention relates to a semiconductor device, a preparation method thereof, and an electronic device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. At present, due to the demand for high device density, high performance, and low cost, the semiconductor industry has advanced to the nanotechnology process node, and the fabrication of semiconductor devices is limited by various physical limits. [0003] As the size of CMOS devices continues to shrink, the short-channel effect has become a key factor affecting device performance. Compared with existing planar transistors, FinFETs are advanced semiconductor devices used for 20nm and below process nodes, which can effective...

Claims

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Application Information

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IPC IPC(8): H01L21/8238H01L27/092
CPCH01L21/823821H01L27/0924H01L29/66803
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP