Semiconductor-laser narrow pulse driving circuit and working method thereof

[0041] Example 1

[0042] Such as figure 1 Shown.

[0043] A semiconductor laser narrow pulse drive circuit includes an external power supply interface circuit, a narrow pulse generation circuit and a MOSFET pulse drive circuit; the external power supply interface circuit supplies power for the narrow pulse generation circuit and the MOSFET pulse drive circuit respectively.

[0044] External power supply interface circuit, used to connect with the external power input terminal to introduce external power; narrow pulse generation circuit, used to generate the required narrow pulse signal, control the MOSFET switch in the MOSFET drive circuit; MOSFET pulse drive circuit, used to drive the laser , Provide the working voltage and working current of the semiconductor laser, and drive the laser to generate the required optical pulse signal.

[0045] Example 2

[0046] As the semiconductor laser narrow pulse driving circuit described in embodiment 1, the difference is that the narrow pulse generating circuit includes a CPLD control chip U6, an AND chip U7, a crystal oscillator clock U8, a delay chip U9, a delay chip U10 and Level conversion chip U11; the MOSFET pulse drive circuit includes a MOSFET drive chip U4;

[0047] Example 3

[0048] Such as Figure 6-11 Shown.

[0049] As in the semiconductor laser narrow pulse driving circuit described in Embodiment 2, the difference is that the second pin of the crystal oscillator clock U8 is connected to the CPLD control chip U6 pin 12, and the crystal oscillator clock U8’s pin 1 is connected to +3.3V Power supply, the 1st pin of the crystal clock U8 is also grounded through the capacitor C13, and the 4th pin of the crystal clock U8 is grounded;

[0050] The 1st and 3rd pins of the level shifting chip U11 are grounded, the 2nd pin of the level shifting chip U11 is connected to +3.3V power supply, and the 4th pin of the level shifting chip U11 is connected to the 26th pin of the CPLD control chip U6 ; Pins 10, 13, and 18 of the level conversion chip U11 are connected in parallel and then connected to +3.3V power; the pins 10, 13, and 18 of the level conversion chip U11 are connected in parallel and grounded through capacitors C14, C15, C16, and C17 respectively ; The 19th pin of the level conversion chip U11 is connected to the 5th pin of the delay chip U10; the 20th pin of the level conversion chip U11 is connected to the 4th pin of the delay chip U10; the 19 of the level conversion chip U11 , Pin 20 is connected to +1.3V power supply through resistor R14 and R13 respectively; Pin 11 of level conversion chip U11 is connected to Pin 5 of delay chip U9; Pin 12 of level conversion chip U11 is connected The 4th pin of the delay chip U9, the 11th and 12th pins of the level conversion chip U11 are connected to the +1.3V power supply through the resistor R15 and the resistor R16 respectively;

[0051] The 1, 2, 23, 25, 26, 27, 29, 30, 31, and 32 pins of the delay chip U10 are connected to the 38, 37, 50, 49, 48, 47, 42, 41, and 41 of the CPLD control chip U6. Pins 40 and 39; pins 3, 9, 10, 11, 12, 16, 24, and 28 of the delay chip U10 are grounded; pin 8 of the delay chip U10 is connected to the delay chip U10 through a resistor R12 The 9th pin is connected; the 13th, 18th, 19th and 22nd pins of the delay chip U10 are connected to +3.3V power; the 20th pin of the delay chip U10 is connected to the No. 2 pin of the AND chip U7; the delay chip The 21st pin of U10 is connected to the 1st pin of the AND chip U7; the 20th and 21st pins of the delay chip U10 are respectively connected to a +1.3V power supply through a resistor R8 and a resistor R10;

[0052] The 8th pin of the delay chip U9 is connected to the 9th pin of the delay chip U9 through the resistor R11; the 9, 10, 12, 16, 24, 28 pins of the delay chip U9 are grounded; the 11 of the delay chip U9 , 13, 18, 19, 22 pins are connected to +3.3V power supply; the 20th pin of the delay chip U9 is connected to the 3rd pin of the AND chip U7; the 21st pin of the delay chip U9 is connected to the AND chip The 4th pin of U7; The 20th and 21st pins of the delay chip U9 are connected to the +1.3V power supply through the resistor R7 and the resistor R9 respectively;

[0053] The 5th pin of the AND chip U7 is grounded; the 6th pin of the AND chip U7 is connected to the MOSFET driver chip U4's 14th, 16th and 20th pins in parallel; the 7th pin of the AND chip U7 is connected to the MOSFET The port where the 15, 17, and 21 pins of the drive chip are connected in parallel; the 7 and 6 pins of the AND chip are connected to +1.3V power through resistors R5 and R6 respectively; the 8 pin of the AND chip U7 is connected to +3.3 V power supply.

[0054] The 4, 8, 10, 12, 24, 26, 28, 29 pins of the MOSFET drive chip U4 are grounded; the 18 and 19 pins of the MOSFET drive chip U4 are connected to the +5V power supply; the 1, 2 of the MOSFET drive chip U4 Pins 3, 5, 6, and 7 are connected in parallel with the adjustable leg of adjustable resistor R2 through resistor R3. The fixed resistance end of adjustable resistor R2 is connected to +5V power supply and ground respectively; MOSFET drive chip U4, 1, Pins 2, 3, 5, 6, and 7 are connected to ground through capacitor C7 after being connected in parallel; Pins 15, 17, and 21 of MOSFET drive chip U4 are connected in parallel to one end of resistor R4, and MOSFET drive chip U4 is connected to 14, 16 , Pin 20 is connected in parallel with the other end of the resistor R4; after the capacitor C1 and the resistor R1 are connected in series, they are connected in parallel with the capacitor C2, the Zener diode D1 and the laser D2 to form a parallel circuit. The MOSFET drives 9, 11, 13, and 13 of the U4 chip. The ports where the pins 23, 25, and 27 are connected in parallel are connected to the +VLD power supply through the parallel circuit. Connect a stable voltage to the CLX terminal of the MOSFET driver chip U4 to control the current flowing through the semiconductor laser.