SoC visual design method based on IP core

Abstract

The invention provides a SoC visual design method based on an IP core. The visual design method comprises the steps of product specification and tool design, system creation, IP-XACT package of the IPcore, visual circuit design and automatic wiring, generation of RTL-level codes, simulation before simulation verification, diagram planning, later simulation and physical verification and the like.The SoC visual design method adopts a visual editing mode to complete the design of an RTL-level previous simulation circuit and thus export the RTL-level codes of hardware description languages, manual RTL-level code compiling is avoided, the speed and efficiency of circuit design are greatly improved, and meanwhile the syntax or function errors because of direct RTL-level code compiling are decreased.

Description

technical field [0001] The invention belongs to the technical field of digital circuit design, in particular to an IP core-based SoC visual design method. Background technique [0002] From the 1990s to the present, IC design capabilities are undergoing a qualitative leap, that is, the transformation from ASIC design methods to SoC design methods. SoC design methods have led to further division of labor in IC design, and IP core design and SoC system design have emerged. , where the IP core in the IP core design may be an IP developed internally by the company, or it may be a third-party IP. In simple terms, the IP can be understood as an ASIC. In the past, the ASIC was completed for others to use on the PCB. Now, after the IP is ready, let others integrate it into a larger chip. After the development of the integrated circuit to the ultra-large-scale stage, the knowledge condensed in the chip has been highly concentrated, and hundreds of millions of transistors are integrat...

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Problems solved by technology

[0002] From the 1990s to the present, IC design capabilities are undergoing a qualitative leap, that is, the transformation from ASIC design methods to SoC design methods. SoC design methods have led to further division of labor in IC design, and IP core design and SoC system design have emerged. , where the IP core in the IP core design may be an IP developed internally by the company, or it may be a third-party IP. In simple terms, the IP can be understood as an ASIC. In the past, the ASIC was completed for others to use on the PCB. Now, after the IP is ready, let others integrate it into a larger chip. After the development of the integrated circuit to the ultra-large-scale stage, the knowledge condensed in the chip has been highly concentrated, and hundreds of millions of transistors are integrated on a single chip. If the chip design is still based on It is almost impossible to design a single transistor rather than an IP-based physical level. The rich IP core module library provides the basic guarantee for quickly designing ASICs and monolithic systems and occupying the market as soon as possible. Reusable IP cores are basically It can be divided into three categories, soft core, solid core and hard core. Soft core is generally implemented by RTL-level description. Its advantage is that it has good flexibility and reusability. The disadvantage is that it has not been optimized and verified at the silicon level. ;The hard core is only provided to the user's functional model and physical wiring model for functional verification and back-end implementation. The real layout implementation is generally provided by the IP supplier to the chip foundry. The solid core is between the soft core and the hard core.

[0003] At present, some EDA tools can help us create advanced algorithm models and simulation models of the entire system using high-level languages ​​such as C and C++ or hardware description language VHDL. Executable documentation. For modules that need to be redesigned, designers need to redesign. For reusable IP cores, usually due to inconsistent bus interface standards, certain modifications need to be made. Since SoC design includes system structure design (also known as Architecture design), software structure design and ASIC design (hardware design), etc. SoC design has become very complicated. In order to quickly and effectively carry out SoC design, IP multiplexing is essential for SoC design. In traditional SoC design, Since the IP core does not have a unified bus interface standard, in most cases, the multiplexing of the IP core often needs to be modified, which brings a certain workload to the circuit designer. Even for the reusable IP core, due to The complexity of SoC design, using a large number of reusable IP cores to build circuit functions is also a very cumbersome thing, which depends very much on the design experience of circuit designers and the level of understanding of hardware description languages, etc., a large number of RTL-level The code is also a very cumbersome event for future development and maintenance. For this reason, the present invention proposes a SoC visual design method based on IP core

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