Non-junction dual-grid line tunneling field-effect transistor

Abstract

The invention belongs to the field of semiconductor devices, and provides a non-junction dual-grid line tunneling field-effect transistor. The non-junction dual-grid line tunneling field-effect transistor is used for improving an on-state current of the non-junction dual-grid line tunneling field-effect transistor. In the tunneling field-effect transistor, P-type doping characteristic source region and an N-type doping characteristic drain region are formed in a non-doped or light-doped channel by electrical doping according to difference between a work function of source region metal and drain region metal and semiconductor electron affinity of a channel region, a vertical symmetric dual-grid structure of a traditional non-junction dual-grid tunneling transistor is changed, so that top-layer metal grid and bottom-layer metal grid are provided with an asymmetric dual-grid structure with length difference, carrier line tunneling is introduced to the non-junction dual-grid tunneling field-effect transistor, and line tunneling is taken as main; and meanwhile, by extending extension length of the top-layer metal grid, the length difference between the top-layer metal grid and the bottom-layer metal grid is increased by shortening the length of the bottom-layer metal grid, the line tunneling area of the transistor is expanded, the carrier tunneling probability is improved, and the on-state current of the device is effectively improved.

Description

technical field [0001] The invention belongs to the field of semiconductor devices and relates to a junctionless tunneling field effect transistor, in particular to a junctionless double gate line tunneling field effect transistor capable of effectively increasing the on-state current. Background technique [0002] With the advancement of integrated circuit technology, the core device in today's VLSI CMOS technology is still MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). As the feature size of MOSFET continues to shrink, the short-channel effect brought Obviously, at the same time, due to the limitation of the working mechanism of MOSFET using carrier drift and diffusion, its subthreshold swing cannot be lower than 60mV / dec at room temperature, thus increasing part of the power consumption of the integrated circuit. [0003] In order to reduce the operating voltage of the device and thereby reduce the power consumption of the integrated circuit, it has become a ...

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Problems solved by technology

However, the carrier tunneling of ordinary junctionless tunneling field-effect transistors occurs at the interface between the source-drain region and the channel region, and the tunneling area is limited, and the on-state current of the device is small; therefore, seeking a It can improve the on-state current of the junctionless tunneling field effect transistor, so that the junctionless tunneling field effect transistor can meet the requirements of the new generation of devices, and it has become a problem to be solved

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