A method for manufacturing gate oxide layer for sic power device chip

Abstract

The invention provides a method for manufacturing a gate oxide layer of a SiC power device chip. The steps include: using a SiC single crystal or an epitaxial wafer, performing multiple P ion implantations on the SiC surface before performing thermal oxidation; Low-temperature annealing; high-temperature thermal oxidation; after thermal oxidation is completed, the temperature is not lowered, and the temperature is directly raised under an atmosphere of an inert gas for high-temperature annealing; after high-temperature annealing, the temperature is rapidly lowered under an atmosphere of an inert gas. This method uses P ion implantation instead of atmosphere to introduce defect elements, and the amount of introduced elements can be precisely controlled through multiple implants. Multiple injections to optimize element distribution ensure that the P injection layer is fully consumed during thermal oxidation. Add NO low-temperature annealing before thermal oxidation, so that P and N elements together form interface traps and reduce the interface state. High-temperature annealing in an inert gas atmosphere without cooling down, directly and rapidly heating up, which is helpful for the by-product CO or CO of SiC thermal oxidation 2 Exclusion reduces the accumulation of C-containing by-products at the interface and improves gate reliability.

Description

technical field [0001] The invention belongs to the technical field of semiconductor chip manufacturing technology, and in particular relates to a method for manufacturing a gate oxide layer of a SiC power device chip. Background technique [0002] With the development of energy saving and emission reduction and smart grid, the performance index and reliability of power semiconductor devices in these fields are increasingly demanding, and there are higher requirements for the operating voltage, current carrying capacity, operating frequency and operating temperature of the device. Require. Due to the characteristics of wide bandgap, high critical breakdown electric field, high thermal conductivity, and high electron saturation drift velocity, SiC materials are especially suitable for making microwave high-power, high-voltage, high-temperature, and radiation-resistant electronic devices. At present, the development of SiC devices has become a Research hotspots. [0003] As ...

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Problems solved by technology

This method can improve the reliability of the gate, but the effect of reducing the interface state density is not obvious;

[0006] 2. Through SiC / SiO 2 The introduction of elements into the interface region forms traps, which can reduce the interface state density, but the introduction of other elements will have a certain impact on the performance of SiC devices

In the prior art, traps are often formed by introducing P elements, but the dosage of P elements cannot be precisely controlled, which results in the formation of P elements and SiO 2 Combined to form phosphosilicate glass (PSG), this substance causes an increase in gate leakage current, which affects the reliability of the device for long-term operation

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