Plate type PECVD system integrated with anti-PID device and passivation film-coating method
A passivation film and plate technology, applied in gaseous chemical plating, coating, photovoltaic power generation, etc., can solve the problems of carrier life reduction, phosphorus redistribution, metal impurities, graphite boat and furnace tube damage, and poor compactness. To achieve the effect of shortening the passivation coating time, reducing the risk of bending, and avoiding thermal shock
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Embodiment 1
[0035] An embodiment of the present invention discloses a plate type PECVD system integrating an anti-PID device, such as Figure 1-3 As shown, along the direction of material transport, it includes a feed bin 1 , an anti-PID device 2 for depositing a passivation film, a PECVD process bin 3 and an outlet bin 4 .
[0036] An anti-PID device is included to provide O 2 Gas cylinder 201, used to induce O 2 produce O 3 The induction device and passivation chamber 206. The induction device is set in the passivation chamber, which can induce O 2 produce O 3 .
[0037] The gas cylinder 201 and the passivation bin 206 are connected by pipelines, and the feeding bin 1 , the passivation bin 206 , the PECVD process bin 3 and the output bin 4 are all equipped with a transmission device 5 .
[0038] During implementation, the material first enters the feed bin 1, and then enters the passivation bin 206 of the anti-PID device, and the O in the gas cylinder 2 Under the induction of the...
Embodiment 2
[0055] Another embodiment of the present invention discloses a passivation coating method. The passivation coating method of this embodiment adopts the plate type PECVD system integrated anti-PID device of embodiment 1, including the following steps:
[0056] Step 1: Silicon wafers enter the feeding bin for the first preheating, preheating to 300-450°C;
[0057] Step 2: The preheated material enters the passivation bin;
[0058] Step 3: Introduce oxygen into the passivation chamber, turn on the UV lamp, and form SiO on the surface of the silicon wafer 2 passivation film;
[0059] Step 4: SiO formation on the surface 2 The silicon wafer with passivation film enters the PECVD process chamber, and the material is preheated for the second time in the heating zone to 300-450°C;
[0060] Step 5: The silicon wafer that has been preheated for the second time passes through the film forming process zone and the cooling zone in sequence.
[0061] Step 6: Silicon wafers enter the dis...
Embodiment 3
[0066] This embodiment discloses an improved passivation coating method, which specifically includes the following steps:
[0067] Step 1: After the silicon wafer goes through the wet etching process, the front door 6 of the feeding bin 1 is opened, the silicon wafer is placed on the graphite frame, and the graphite frame enters the feeding bin 1 through the transmission device 5, and the front end of the feeding bin 1 The warehouse door 6 is closed;
[0068] Step 2: Vacuumize the feeding bin, and at the same time, the infrared heater in the feeding bin preheats the silicon wafer in the first step, and controls the temperature of the silicon wafer at 300°C to 450°C;
[0069] Step 3: After preheating, the bin door 6 between the feeding bin 1 and the passivation bin 206 is opened, and the silicon wafer enters the passivation bin 206 in the PID device 2 through the transmission device 5. After the silicon wafer enters, the feeding bin 1 and the chamber door 6 between the passiva...
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