Front grid line passivation contact-based PERC solar cell and preparation method thereof
A technology of solar cells and front grid lines, applied in circuits, photovoltaic power generation, electrical components, etc., can solve the problems of serious light parasitic absorption, battery short-circuit current loss, etc., to reduce carrier recombination, reduce body life and efficiency loss. , the effect of improving efficiency
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Embodiment 1
[0034] Such as figure 1 As shown, a PERC solar cell with passivation contact on the front gate line includes a P-type monocrystalline silicon substrate 1, and the back of the P-type monocrystalline silicon substrate 1 is sequentially provided with a back aluminum oxide passivation layer 2 and a back surface from the inside to the outside. Silicon nitride passivation layer 3, the front of P-type single crystal silicon substrate 1 is provided with front silicon oxide passivation layer 4 and front silicon nitride passivation layer 5 sequentially from inside to outside, and the front of P-type single crystal silicon substrate 1 is provided with There is a front metal silver grid line 6 that runs through the front silicon oxide passivation layer 4 and the front silicon nitride passivation layer 5, and it is characterized in that the front side of the P-type single crystal silicon substrate 1 is located on the front metal silver grid line 6 An ultra-thin tunneling silicon oxide laye...
Embodiment 2
[0040] A kind of preparation method of the PERC solar cell that the front grid line passivation contact of preparation embodiment 1 comprises the following steps,
[0041] 1) Texture making: use P-type monocrystalline silicon wafer as the substrate, place it in the texturing solution to make pyramid texture, and then clean the surface of the silicon wafer in a hydrofluoric acid solution with a volume concentration of 1-10% ,
[0042] 2) Preparation of ultra-thin tunneling silicon oxide layer: prepare a layer of ultra-thin tunneling silicon oxide on the front and back of the single crystal silicon substrate at the same time, the thickness of the tunneling silicon oxide is 1-2nm,
[0043] 3) Preparation of phosphorus-doped polysilicon layer: using LPCVD equipment to simultaneously deposit a layer of phosphorus-doped phosphorus-doped polysilicon layer on the ultra-thin tunneling silicon oxide on the front and back of the single crystal silicon substrate, with a thickness of 100-3...
Embodiment 3
[0053] A method for preparing the PERC solar cell with passivation contact on the front side of the gate line in Example 1, using a P-type single crystal silicon wafer as a substrate, and performing conventional texturing. After hydrofluoric acid and RCA standard cleaning, a layer of ultra-thin tunneling silicon oxide with a thickness of 1-2nm is simultaneously prepared on the front and back of the silicon substrate, and then a layer of ultra-thin tunneling silicon oxide is simultaneously deposited on the front and back of the silicon substrate by LPCVD equipment. Phosphorus-doped amorphous / microcrystalline silicon layer with a layer thickness of 100-300 nm. A mask is deposited on the front side of the silicon substrate by APCVD or PECVD, and then a corrosion-resistant ink consistent with the pattern of the front metal grid line is printed on the mask. The mask of the non-ink protection area is removed in a hydrofluoric acid solution with a volume concentration of 1-10%, and t...
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