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High-barrier SiC JBS device and preparation method thereof

A device and high-potential technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as large chip reverse leakage

Pending Publication Date: 2021-02-02
ZHUZHOU CRRC TIMES SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to provide a high potential barrier SiC JBS device and its preparation method to solve the problem of large reverse leakage of SiC JBS chips with high current density.

Method used

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  • High-barrier SiC JBS device and preparation method thereof
  • High-barrier SiC JBS device and preparation method thereof
  • High-barrier SiC JBS device and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0102] Such as Figure 1f As shown, the high barrier SiC JBS device provided in this embodiment includes a first electrode layer, a SiC substrate, an N-SiC epitaxial layer, a second electrode layer, a dielectric layer and a PI layer arranged from top to bottom.

[0103] Among them, the first electrode layer uses Ni as the SiC ohmic alloy layer, and the Ti / Ni / Ag back metal layer is thickened, with a thickness of 1.0um-1.2um; the thickness of the SiC substrate is 250um-350um; the N-SiC epitaxial layer The thickness is 6um-30um, which is doped with nitrogen ions and phosphorus ions, and the doping concentration is 1e15cm -3 -3e16cm -3 ; The second electrode layer is a Ti metal layer with a thickness of 150nm-200nm; the dielectric layer is SiO 2 The thickness of the layer is 0.8um-1.0um; the thickness of the PI layer is 10um-30um.

[0104] The N-SiC epitaxial layer includes a junction barrier region extending from the upper surface of the epitaxial layer into the epitaxial laye...

Embodiment 2

[0123] The structure of the high barrier SiC JBS device provided in this example is the same as that of Example 1, and its preparation method is as follows:

[0124] Step 1: providing a SiC substrate and an N-SiC epitaxial layer on the SiC substrate;

[0125] Step 2: forming a junction barrier region and a terminal region on the upper surface of the epitaxial layer:

[0126] (1) Cleaning the N-SiC wafer;

[0127] (2) An etching mask is grown on the surface of the SiC wafer, and a second mask is used to perform photolithography and etching to form a second implant mask, and a deep implantation of P-type impurities (P+ implantation) is performed on the etched area, The depth of injection is 1.0um, and the injection concentration is 1e19cm -3 -5e20cm -3 , forming a JBS structure;

[0128] (3) Remove the mask and clean the wafer;

[0129] (4) An etching mask is grown on the surface of the wafer in step (3), and the active region is photolithographically and etched using the f...

Embodiment 3

[0133] The structure of the high barrier SiC JBS device provided in this example is the same as that of Example 1, and its preparation method is as follows:

[0134] Step 1: providing a SiC substrate and an N-- / N-SiC epitaxial layer on the SiC substrate;

[0135] Step 2: forming a junction barrier region and a terminal region on the upper surface of the epitaxial layer:

[0136] (1) Clean the N-- / N-SiC wafer;

[0137] (2) Growing an etching mask on the surface of the SiC wafer, using the second mask plate, performing photolithography and etching to form a second implant mask, and performing deep implantation of P-type impurities (P+ implantation) into the etched area, The depth of injection is 1.0um, and the injection concentration is 1e19cm -3 -5e20cm -3 , forming a junction barrier region in the active region and forming a terminal region at the same time;

[0138] (3) Remove the mask, clean the wafer, and perform annealing treatment.

[0139] Step 3-6: Same as Example ...

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Abstract

The invention discloses a high-barrier SiC JBS device and a preparation method thereof. The device comprises a first electrode layer, a SiC substrate, an N-SiC epitaxial layer, a second electrode layer, a dielectric layer and a PI layer which are arranged from top to bottom. According to the SiC device, a JBS structure and a surface low-concentration structure are formed on the epitaxial layer, sothat the barrier height of the device is increased, and meanwhile, the electric leakage characteristic of the device is reduced.

Description

technical field [0001] The invention relates to a high potential barrier SiC JBS device and a preparation method thereof, belonging to the field of semiconductor device manufacturing. Background technique [0002] Silicon carbide (SiC), as the third-generation wide-bandgap semiconductor material, has the characteristics of high electron saturation velocity, high pressure resistance, radiation resistance, and high temperature resistance, which make up for the traditional silicon materials in high power density, high temperature, and high temperature. Deficiencies in the field of high-frequency applications. This makes SiC-based power semiconductor devices, especially SiC SBD devices with high current density, one of the hottest research topics in the SiC field. [0003] SiC JBS (Silicon Carbide Junction Barrier Diode) structure devices have become the mainstream design scheme of SiC SBD devices due to their high reverse withstand voltage. Because the forward current charact...

Claims

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Application Information

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IPC IPC(8): H01L29/861H01L29/06H01L21/328
CPCH01L29/8618H01L29/0603H01L29/0684H01L29/6609
Inventor 罗烨辉周正东李诚瞻
Owner ZHUZHOU CRRC TIMES SEMICON CO LTD
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