Silicon carbide trench MOSFET device structure and processing method
A device structure, silicon carbide trench technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as material defects, and achieve the effect of reducing electric field strength, improving reliability, and good breakdown voltage
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Embodiment 1
[0062] Such as figure 1 As shown, a silicon carbide trench MOSFET device structure, MOSFET is a metal-oxide semiconductor field effect transistor, including: silicon carbide N+ substrate 1, silicon carbide epitaxial N region 2, P well region 3, P+ region 4, N+ Region 5, oxide layer 6, gate 7, gate oxide 8, front metal 9, back drain 10 and source 11; silicon carbide N+ substrate 1 grows silicon carbide epitaxial N region 2, silicon carbide epitaxial N region 2 The gate 7 and gate oxide 8 are arranged on the upper side, the gate oxide 8 is arranged on the outer part of the gate 7, the oxide layer 6 is grown on the upper side of the gate 7, the P well region 3 is arranged on both sides of the gate 7, and the upper side and the side surface of the P well region 3 Set the N+ region 5, set the P+ region 4 on the P well region 3, set the source 11 on the P well region 3, the P+ region 4 and the N+ region 5, set the front metal 9 on the source 11 and the gate 7, silicon carbide A bac...
Embodiment 2
[0066] Embodiment 2 is a preferred example of Embodiment 1.
[0067] Such as figure 1 As shown, this embodiment includes a silicon carbide N+ substrate 1, and a silicon carbide epitaxial N region 2 grown on the silicon carbide N+ substrate 1; a gate oxide 8 and a gate 7 are arranged on the silicon carbide epitaxial N region 2, An oxide layer 6 as an isolation layer is grown on the gate 7, and symmetrically arranged P well regions 3 are respectively arranged on both sides of the gate 7, and N+ regions 5 are arranged on the top and side surfaces of the P well region 3; A P+ region 4 is set above the first P well region; a source electrode 11 is provided above the P well region 3, P+ region 4 and N+ region 5; interconnection is provided on the source electrode 11 and the gate electrode 7 on both sides. metal 9 on the front side, and a drain 10 on the back side of the silicon wafer.
[0068] The specific processing steps are as follows:
[0069] First, a silicon carbide epitaxi...
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