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Silicon carbide trench MOSFET device structure and processing method

A device structure, silicon carbide trench technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as material defects, and achieve the effect of reducing electric field strength, improving reliability, and good breakdown voltage

Pending Publication Date: 2022-02-01
北京绿能芯创电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] None of the above patents can solve the problem of material defect characteristics caused by the electric field concentration and implantation of the SiC interface gate oxide of the silicon carbide material

Method used

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  • Silicon carbide trench MOSFET device structure and processing method
  • Silicon carbide trench MOSFET device structure and processing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0062] Such as figure 1 As shown, a silicon carbide trench MOSFET device structure, MOSFET is a metal-oxide semiconductor field effect transistor, including: silicon carbide N+ substrate 1, silicon carbide epitaxial N region 2, P well region 3, P+ region 4, N+ Region 5, oxide layer 6, gate 7, gate oxide 8, front metal 9, back drain 10 and source 11; silicon carbide N+ substrate 1 grows silicon carbide epitaxial N region 2, silicon carbide epitaxial N region 2 The gate 7 and gate oxide 8 are arranged on the upper side, the gate oxide 8 is arranged on the outer part of the gate 7, the oxide layer 6 is grown on the upper side of the gate 7, the P well region 3 is arranged on both sides of the gate 7, and the upper side and the side surface of the P well region 3 Set the N+ region 5, set the P+ region 4 on the P well region 3, set the source 11 on the P well region 3, the P+ region 4 and the N+ region 5, set the front metal 9 on the source 11 and the gate 7, silicon carbide A bac...

Embodiment 2

[0066] Embodiment 2 is a preferred example of Embodiment 1.

[0067] Such as figure 1 As shown, this embodiment includes a silicon carbide N+ substrate 1, and a silicon carbide epitaxial N region 2 grown on the silicon carbide N+ substrate 1; a gate oxide 8 and a gate 7 are arranged on the silicon carbide epitaxial N region 2, An oxide layer 6 as an isolation layer is grown on the gate 7, and symmetrically arranged P well regions 3 are respectively arranged on both sides of the gate 7, and N+ regions 5 are arranged on the top and side surfaces of the P well region 3; A P+ region 4 is set above the first P well region; a source electrode 11 is provided above the P well region 3, P+ region 4 and N+ region 5; interconnection is provided on the source electrode 11 and the gate electrode 7 on both sides. metal 9 on the front side, and a drain 10 on the back side of the silicon wafer.

[0068] The specific processing steps are as follows:

[0069] First, a silicon carbide epitaxi...

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Abstract

The invention provides a silicon carbide trench MOSFET device structure and a processing method. The silicon carbide trench MOSFET device structure comprises a silicon carbide N+ substrate, a silicon carbide epitaxial N region, a P well region, a P+ region, an N+ region, an oxide layer, a gate electrode, gate oxide, front metal and a source electrode; a silicon carbide epitaxial N region grows on the upper side of the silicon carbide N+ substrate; the gate electrode and the gate oxide are arranged on the upper side of the silicon carbide epitaxial N region, and the gate oxide is arranged outside the gate electrode; the oxide layer grows on the upper side of the gate electrode, and the P well regions are arranged on two sides of the gate; N+ regions are arranged on the upper side and the side face of the P well region, and P+ regions are arranged on the P well region; source electrodes are arranged on the upper sides of the P well region, the P+ region and the N+ region; and the front metal is arranged on the source electrode and the gate electrode. According to the design, the peak electric field under the gate electrode is transferred to the source electrode when the device works through the trench structure arranged in the source region and the multi-layer epitaxial process, and the peak electric field under the gate electrode is reduced, so that the higher electric field intensity borne by the gate oxide can be effectively reduced, the gate oxide layer is prevented from being broken down in advance, and the device obtains better breakdown voltage.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a device structure and a processing method of a silicon carbide trench MOSFET. Background technique [0002] SiC (silicon carbide) is a compound semiconductor material composed of silicon (Si) and carbon (C), which has superior electrical properties, including a wide band gap (2.3-3.3eV), which is 3 times that of Si; high breakdown Field strength (0.8E16~3E16V / cm), 10 times that of Si; high saturation drift velocity (2E7cm / s), 2.7 times that of Si; and high thermal conductivity (4.9W / cmK), about 3.2 times that of Si. Therefore, the third-generation semiconductor-SIC (silicon carbide) has become an ideal semiconductor material for high-temperature, high-frequency, radiation-resistant and high-power power electronic devices due to its high band gap, high blocking voltage and high thermal conductivity. Among them, silicon carbide metal oxide semiconductor field effect...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L29/423H01L29/78H01L21/336H01L21/28
CPCH01L29/7827H01L29/66068H01L29/0684H01L29/0623H01L29/401H01L29/42356H01L29/4236
Inventor 不公告发明人
Owner 北京绿能芯创电子科技有限公司
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