Low-power-consumption field effect transistor and preparation method thereof
A power consumption field and transistor technology, which is applied in the field of preparation of low power consumption organic field effect transistors, can solve problems such as power consumption reduction, and achieve the effects of ultra-low power consumption, low electrolysis risk, and low operating voltage
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Embodiment 1
[0056] The highly doped silicon wafers were ultrasonically cleaned in soapy water, deionized water, acetone and ethanol for 20 min, and then washed with N 2 blow dry. The polymethacryloyl ethyl betaine trifluoroethanol solution (30mg / mL) was spin-coated on the washed silicon substrate (rotating speed 2000r / min, time 60s), under N 2 Anneal at 100°C for 30min in the environment, and then apply polymethyl methacrylate (PMMA) ethyl acetate solution (50mg / mL) under the same spin coating conditions. then in N 2 Anneal at 100°C for 30 minutes in the environment, and use an evaporation device to Evaporate 50nm thick 2,7-dioctylbenzo[LMN][3,8]phenanthroline-1,3,6,8-(2H,7H)-tetraketone (bilateral C8) semiconductor layer . Finally, using an evaporator to A 50 nm-thick Au electrode (size: 5600×200 μm) was prepared on the dielectric layer by mask plate deposition at a rate of . The power consumption of the obtained transistor was measured by a semiconductor parameter tester (Keit...
Embodiment 2
[0058] The highly doped silicon wafers were ultrasonically cleaned with soapy water, deionized water, acetone and ethanol for 20 min, and dried with nitrogen. Drop 30 mg / mL polymethacryloyl ethyl betaine trifluoroethanol solution onto the above-mentioned washed silicon wafer, and spin coat at a speed of 2000 r / min for 1 min. Then, put the sample in N 2 Anneal at 100°C for 30min in the environment, and then spin-coat 50mg / mL polymethyl methacrylate ethyl acetate solution under the same conditions. Then put it in a nitrogen environment, anneal at 100°C for 30min, and then use an evaporation device to Evaporate 50 nm-thick pentacene as the semiconducting layer at a rate of . Finally, an Au electrode (size: 5600×200 μm) was evaporated on the surface of the sample. The resulting transistor operates with a power dissipation of 0.20 fJ.
Embodiment 3
[0060] First, the highly doped silicon wafers were cleaned with soapy water, deionized water, acetone and ethanol in an ultrasonic cleaner for 20 min, and then N 2 blow dry. Polymethacryloyl ethyl betaine was dissolved in trifluoroethanol to obtain a solution with a concentration of 30mg / mL, and the solution was spin-coated on a silicon wafer at a speed of 2000r / min for 60s, and then placed in a glove box Anneal at 100°C for 30min. followed by Evaporate 50 nm of pentacene as a semiconducting layer at a rate of Finally, a 50 nm Au electrode (5600 × 200 μm) was placed in The rate is deposited on the semiconductor layer through the mask. The power dissipation of the transistor was measured as low as 2.22fJ.
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