Method for preparing focal plane of quantum trap infrared detecter

Abstract

The invention is a method for preparing focal plane (FPA) of a quantum well infrared probe (QWIP), starting with two heterogeneous wafers, silicon wafer and GaAs wafer, where the silicon wafer and the GaAs wafer are made with a silicon-base read integrated circuit, and terminating layer, lower electrode layer, quantum well layer, upper electrode layer, and 2D grating, respectively; firstly using the chemical-mechanical flattening process to make the surface of the silicon wafer smooth, flat and clean and then aligning the upper electrodes of the smooth, flat and clean GaAs wafer with the corresponding metallic electrodes on the silicon wafer, using low-temperature heterogeneous wafer bonding method to bond the two wafers and make low-temperature thermal treatment until they are bonded together, then thinning the substrate of the GaAs wafer, selectively eating off the residual substrate, using corrosive solution to eat off the terminating layer, and finally completing the connection between the QWIP and the corresponding electrodes of the silicon-base read integrated circuit to obtain the productí¬FPA of QWIP. The method has the advantages of low cost, strong mechanical strength and good reliability.

Description

technical field [0001] The invention relates to a preparation method of a focal plane (FPA) of a quantum well infrared detector (QWIP). To be precise, it relates to a method for preparing QWIP-FPA by direct low-temperature heterogeneous bonding of QWIP and silicon-based readout integrated circuit (ROIC). It belongs to the field of optoelectronic integration technology. Background technique [0002] Due to the application of quantum well infrared detector (QWIP) focal plane (FPA) technology in meteorology, astronomy, earth observation, night vision, navigation, aircraft control, early warning system and other commercial, industrial and military fields, large-scale QWIP-FPA demand is growing. However, a large-scale QWIP-FPA is a complete FPA device formed by a large-scale QWIP photosensitive element array and a silicon-based readout signal integrated circuit, which are directly or indirectly interconnected through indium pillars grown separately. Th...

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Problems solved by technology

[0004] 1. QWIP-ROIC adopts the method of direct upside-down interconnection or indirect upside-down interconnection method, under the action of repeated thermal cycle load of 300-30K cycles, the thermal expansion of the three materials of indium column, GaAs substrate of QWIP array and silicon-based ROIC Coefficient (CTE) mismatch, large stress changes cause viscoplastic deformation of indium pillars, causing indium pillar solder joints to fall off, crack, etc., leading to performance degradation or even failure of QWIP FPA

[0005] 2. There are two major difficulties in heteroepitaxial monolithic integration or local heteroepitaxial monolithic integration: 1) III-V materials such as silicon and GaAs have a 4% lattice mismatch, resulting in high fault density

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