High-density inter-die interconnect structure

a high-density, inter-die technology, applied in the direction of diodes, radiation controlled devices, semiconductor devices, etc., can solve the problems of high operating voltage, increased system cost and size, and unsuitable ccd arrays for integration,

Inactive Publication Date: 2006-07-27
BELL SEMICON LLC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This separation allows for improved image sensor sensitivity, dynamic range, and color balance while reducing system size and power consumption, enhancing the overall efficiency and reliability of the image sensor array.

Problems solved by technology

Due to voltage, capacitance and process constraints, CCD arrays are not well suited to integration at the high levels of integration possible in CMOS integrated circuits.
As a result, the system cost and size are increased.
It is also known that CCD image sensors require a large power consumption and higher operating voltages, as compared with conventional CMOS signal processing circuitry.
Larger junctions collect more photons and are more sensitive to light, but larger junctions also reduce the resolution of a sensor because fewer pixels can be placed on the available surface area.
CMOS image sensors are formed with the same CMOS process technology used for the associated circuitry required to operate the CMOS image sensor and therefore the sensors and support circuitry are easily integratible into a single chip.
Also, CCD image sensors lack a consistent dark level voltage due to fabrication processing imperfections.
However, CMOS image sensors are not without disadvantages.
The use of state-of-the-art CMOS integrated circuit fabrication techniques for the associated signal processing circuitry, and the CMOS image sensor would compromise the construction of the CMOS photo sensors, thereby reducing the image signal quality.
Reducing the doping levels to achieve better sensor sensitivity, dynamic range, or color balance, would significantly degrade the performance of the CMOS processing circuitry.
Therefore, higher levels of component integration (i.e., image sensors and operative signal processing circuitry on the same chip) are therefore not practical.
Further, in those situations where the CMOS image sensor and its signal processing circuitry are co-located on the same integrated circuit, the associated circuits consume a portion of the available pixel area, resulting in a larger overall chip area and reducing the image fill factor (the ratio of the active pixel area to the total pixel area).
The efficiency, resolution and sensitivity of the CMOS image sensor array is in turn disadvantageously reduced.
Also, certain CMOS material layers (e.g., salicide layers) may be partially or completely opaque, reducing the image sensor sensitivity.
Although removal of these process steps improves image sensor signal quality, the CMOS technology is generally compromised.

Method used

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Embodiment Construction

[0017] The processing steps and hardware components of the present invention have been represented by conventional processes and elements in the drawings, showing only those specific details that are pertinent to the present invention so as not to obscure the disclosure with details that will be readily apparent to those skilled in the art having the benefit of the description herein. Exemplary device layers are not shown to scale. Like reference characters represent like structures elements throughout.

[0018] Bulk semiconductor materials can be used as photo conductors (also referred to as photo sensors or image sensors) based on the change in the semiconductor resistance as a function of the wavelength and intensity of the impinging light waves. Electrons in bound states in the valence band (for intrinsic semiconductor material) or in doping-determined energy levels within the forbidden band gap (for extrinsic semiconductor materials) absorb energy from the incident light photons ...

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Abstract

An interconnect architecture for connecting a plurality of closely-spaced electrical elements on a first integrated circuit fabricated structure with operative circuits on a second integrated circuit fabricated structure. In one embodiment, the first integrated circuit fabricated structure comprises a plurality of photo sensors. Conductive interconnect elements on the first integrated circuit fabricated structure provide electrical connection between individual photo sensors and the operative circuitry on the second integrated circuit fabricated structure.

Description

[0001] This patent application is a divisional application of and claims the benefit of the U.S. patent application assigned Ser. No. 10 / 638,248 and filed on Aug. 8, 2003, which is a continuation application of and claims the benefit of the U.S. patent application assigned Ser. No. 09 / 950,387 and filed on Sep. 10, 2001.FIELD OF THE INVENTION [0002] The present invention is directed to an interconnect structure for semiconductor die and, more specifically, the invention relates to an interconnect structure for die where the circuits on at least one die are separately and independently operable and closely spaced. BACKGROUND OF THE INVENTION [0003] Various types of imagers or image sensors are in use today, including charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors. These semiconductor-based image sensors are widely used in many image input devices because they can be mass produced using advanced fine-patterning lithographic te...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L21/00H01L21/60H01L25/065H01L25/18H01L25/07H01L27/146
CPCH01L24/81H01L27/1464H01L27/14621H01L27/14634H01L27/14636H01L27/14643H01L27/1465H01L27/1469H01L2224/16145H01L2224/81801H01L2924/01033H01L2924/01057H01L2924/01058H01L2924/0106H01L2924/01079H01L2924/01082H01L2924/14H01L2924/19043H01L2924/30105H01L2924/01005H01L2924/01006H01L2924/01023H01L2924/01037H01L2924/0105H01L2924/01075H01L2924/014H01L2924/12032H01L27/14618H01L2924/00H01L2924/12036H01L27/146H04N25/76
InventorLAYMAN, PAUL ARTHURMCMACKEN, JOHN RUSSELL
OwnerBELL SEMICON LLC