Reduced electric field DMOS using self-aligned trench isolation

Abstract

A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This is a divisional of pending application Ser. No. 11 / 188,921 filed Jul. 25, 2005.TECHNICAL FIELD[0002]The invention relates to electronic semiconductor devices and methods of fabrication, and, more particularly, to semiconductor devices and fabrication methods thereof for reducing electric fields and other deleterious effects by using self-aligned trench isolation techniques.BACKGROUND ART[0003]The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon die. As the number of electronic devices per given area of a silicon wafer increases, manufacturing processes employed become more difficult.[0004]An important subject of ongoing research in the semiconductor industry is a reduction in the dimensions of devices used...

AI Technical Summary

Benefits of technology

[0015]Due to the aforementioned attributes and processing methods, the present invention is, inter alia, capable of attaining a higher isolation voltage between gate and drift regions than the prior art without degrading a trajectory of injected carriers or forcing them deeper into the body of the device. Also, the structure of the resulting device allows for a greatly reduced capacitance between the device gate and drift region with an elimination of the “gate wrap-around,” thereby reducing a local electric field.

Problems solved by technology

As the number of electronic devices per given area of a silicon wafer increases, manufacturing processes employed become more difficult.

This increased parasitic resistance degrades the switching speed and current carrying capabilities of the transistor.

The necessity of LDD regions also adds process steps to fabrication which negatively affect both cost and reliability.

The wide channel region formed in such a process contributes undesirable characteristics to a transistor's performance.

The gate wrap-around region 115, however, has at least the following detrimental affects to MOS device performance: (1) isolation voltages between gate and drift regions of a device are reduced; and (2) the divot produces a high capacitance region between the gate and drift regions, thereby creating a high local-electric field.

Images