CMOS device comprising mos transistors with recessed drain and source areas and non-conformal metal silicide regions

Abstract

A non-conformal metal silicide in a transistor of recessed drain and source configuration may provide enhanced efficiency with respect to strain-inducing mechanisms, drain/source resistance and the like. For this purpose, in some cases, an amorphizing implantation process may be performed prior to the silicidation process, while in other cases an anisotropic deposition of the refractory metal may be used.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to high performance transistors having recessed drain and source regions and strained channel regions by using stress sources, such as stressed overlayers, to enhance charge carrier mobility in the channel region of a MOS transistor.[0003]2. Description of the Related Art[0004]Generally, a plurality of process technologies are currently practiced in the field of semiconductor production, wherein, for complex circuitry, such as microprocessors, advanced storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and / or power consumption and / or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a sub...

AI Technical Summary

Benefits of technology

[0013]Generally, the present disclosure relates to techniques and semiconductor devices in which drain and/or source resistance in recessed transistor configurations may be enhanced by adapting a thickness profile of a metal silicide layer formed on exposed surface portions of a recessed drain region and/or source region. Contrary to conventional strategies for forming metal silicide regions, in which a substantially uniform layer thickness and thus a substantially conformal metal silicide layer may be provided in the drain and source regions, the present disclosure contemplates a non-conformal silicidation process, at least in one of the drain and source regions of at least one type of transistor, thereby enabling a reduction of the metal silicide thickness at substantially vertical surface portions within the recess, while nevertheless maintaining a desired increased thickness at substantially horizontal portions, i.e., at the bottom of the recesses. Consequently, an overall increased area for accepting charge carriers from the channel regions may still be provided, thereby reducing the resistance for “spreading” the drain/source current while, on the other hand, the thickness and thus the distance of metal silicide from the channel region in the vicinity of the gate insulation laye

Problems solved by technology

The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors.

One major problem in this respect is providing low sheet and contact resistivity in drain and source regions and any contacts connected thereto and maintaining channel controllability.

Presently, the thickness of silicon dioxide based gate insulation layers is in the range of 1-2 nm, wherein a further reduction may be less desirable in view of leakage currents which typically exponentially increase when reducing the gate dielectric thickness.

It turns out, however, that the internal stress levels of silicon nitride material may be restricted by the overall deposition capabilities of presently available plasma enhanced CVD techniques, while also the effective layer thickness may be substantially determined by the basic transistor topography and the distance between neighboring circuit elements.

Consequently, although providing significant advantages, the efficiency of the stress transfer mechanism may significantly depend on process and device specifics and may result in reduced

Images