Silicon-on-insulator wafer and low temperature method to make thereof

Abstract

A process for making silicon on insulator wafer by bond and etch back—BESOI. Fluorine ion implantation is performed after bonding and after removal of etch stop layers. The ion energy is chosen to have a peak of ion distribution near the wafer bonding interface. The ion dose is chosen to exceed silicon amorphization threshold at maximum ion distribution. The ion dose is chosen low enough to keep silicon surface crystalline. Solid phase epitaxy SPE is performed after the implant. Finalizing of wafer bonding is performed after the SPE by anneal at 800 C. SPE is performed by anneal where temperature is slow ramped up from 450 to 600 C. In further chipmaking process, defect generation as oxidation induced stacking faults—OISFs—during oxidation step is prevented. OISF are not generated even in metal contaminated wafers. As process does not includes high temperature anneal, RF SOI devices—like front chips of smartphones—made on these wafers have advanced RF performance. Process uses only standard equipment readily available at semiconductor foundries; therefore, the process can be easily implemented at foundries.

Description

REFERENCE TO RELATED APPLICATIONS[0001]This application claims an invention which was disclosed in Provisional Application No. 63 / 005,389, filed Apr. 5, 2020, entitled “Silicon-on-insulator wafer and low temperature method to make thereof”. The benefit under 35 USC § 119(e) of the United States provisional application is hereby claimed, and the aforementioned application is hereby incorporated herein by reference.BACKGROUND OF THE INVENTIONField of the Invention[0002]The invention relates to methods of making silicon on insulator—SOI-wafers that can be further used for making chips. Preferably it is for making SOI wafers for radio frequency—RF applications, for example, for front end chips of smart phones.Description of Related Art[0003]Silicon on insulator—SOI-wafers are used as a starting material to make integrated circuits in cases when cheaper bulk silicon wafers cannot be used. For example, SOI used to make front end chips for cell phones. These are mixed signal chips and need...

AI Technical Summary

Benefits of technology

The patent describes a process for making silicon-on-insulator (SOI) wafers by growing a layer of silicon on a sacrificial wafer. A layer of silicon dioxide is then deposited on top of the silicon layer. Fluorine ions are implanted into the silicon dioxide to improve its quality and prevent the formation of defects that can affect the performance of the final chips. The process also includes steps to enhance the bonding of the silicon layer to the insulator and to prevent the growth of additional layers that may affect the uniformity of the final chip. The use of fluorine implantation in the process has been found to lead to improved performance and yield of final chips made on the SOI wafers.

Problems solved by technology

These are mixed signal chips and need to work at high frequencies of several gigahertz, therefore they cannot be made on bulk silicon wafers.

However, in the art there is no method of making SOI wafer that use standard tools only that are readily available at foundries.

The major problem was high defect density in its cap silicon film.

The bigger defect size is, the higher probability that it will become a killer defect.

During CMOS chipmaking, OISF forms during gate oxidation or other oxidation steps and causes GOI—gate oxide integrity failure.

Thus, the final chip malfunctions and the chips get rejected.

It requires specialized equipment that is not available at a typical foundry.

Also, wafer cleaving step in Smart-Cut requires a special tool that is not commercially available.

The bonding interface has defects that negatively affect performance of final chips.

This way is not applicable for RF SOI-wafer that has an additional polysilicon layer below BOX and high resistivity handle wafer.

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