Silicon-on-insulator wafer and low temperature method to make thereof

a technology of silicon-on-insulator wafers and low temperature methods, which is applied in the direction of semiconductor/solid-state device manufacturing, basic electric elements, electric apparatus, etc., can solve the problems of high defect density of silicon film caps, inability to make bulk silicon wafers, and inability to use standard tools to make soi wafers. achieve the effect of high chip yield and high tolerance to metal contamination
US20220319911A1Active Publication Date: 2022-10-06USENKO ALEXANDER YURI
6 Cites 0 Cited by

Patent Information

Authority / Receiving Office
US ¡ United States
Patent Type
Applications(United States)
Current Assignee / Owner
USENKO ALEXANDER YURI
Publication Date
2022-10-06

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

A process for making silicon on insulator wafer by bond and etch back—BESOI. Fluorine ion implantation is performed after bonding and after removal of etch stop layers. The ion energy is chosen to have a peak of ion distribution near the wafer bonding interface. The ion dose is chosen to exceed silicon amorphization threshold at maximum ion distribution. The ion dose is chosen low enough to keep silicon surface crystalline. Solid phase epitaxy SPE is performed after the implant. Finalizing of wafer bonding is performed after the SPE by anneal at 800 C. SPE is performed by anneal where temperature is slow ramped up from 450 to 600 C. In further chipmaking process, defect generation as oxidation induced stacking faults—OISFs—during oxidation step is prevented. OISF are not generated even in metal contaminated wafers. As process does not includes high temperature anneal, RF SOI devices—like front chips of smartphones—made on these wafers have advanced RF performance. Process uses only standard equipment readily available at semiconductor foundries; therefore, the process can be easily implemented at foundries.
Need to check novelty before this filing date? Find Prior Art

Description

REFERENCE TO RELATED APPLICATIONS

[0001] This application claims an invention which was disclosed in Provisional Application No. 63 / 005,389, filed Apr. 5, 2020, entitled “Silicon-on-insulator wafer and low temperature method to make thereof”. The benefit under 35 USC § 119(e) of the United States provisional application is hereby claimed, and the aforementioned application is hereby incorporated herein by reference.BACKGROUND OF THE INVENTIONField of the Invention

[0002] The invention relates to methods of making silicon on insulator—SOI-wafers that can be further used for making chips. Preferably it is for making SOI wafers for radio frequency—RF applications, for example, for front end chips of smart phones.Description of Related Art

[0003] Silicon on insulator—SOI-wafers are used as a starting material to make integrated circuits in cases when cheaper bulk silicon wafers cannot be used. For example, SOI used to make front end chips for cell phones. These are mixed signal chips and need...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More