Semiconductor on insulator (SOI) lateral metal-oxide-semiconductor field-effect-transistor (MOSFET) device and integrated circuit

Abstract

A silicon-on-insulator (SOI) lateral MOSFET device and the integrated circuit thereof are provided. In said device, an active layer (3) includes a body region (9) and a drain region (12) which are located on the surface of the active layer (3) respectively and are separated from each other, and also a planar gate channel region (14'), a source region (11a), a body contact region (10) and a source region (11b) which are located on the surface of the body region (9) and are set in sequence from the side adjacent to the drain region (12). The active layer (3) located between the body region (9) and the drain region (12) is a drift region, wherein the drift region and the body region (9) have opposite conduction types. A semiconductor buried layer (4) is set beneath the surface of the active layer (3), wherein the semiconductor buried layer (4) and the body region (9) have the same conduction type. Said device has a trench gate structure (8) and a planar gate structure (8'), wherein the trench gate structure (8) contacts with the body region (9) and longitudinally extends from the surface of the active layer (3) to a dielectric buried layer (2), and the planar gate structure (8') is formed above the body region (9). Said device has the advantages of high withstand voltage, low specific on-resistance, low power consumption, low cost, and easy miniaturization and integration.

Description

technical field [0001] The present invention relates to semiconductor power devices and integrated circuits, in particular to a SOI (Semiconductor On Insulator, semiconductor on insulating substrate) lateral MOSFET (Metal-Oxide-Semiconductor Field-Effect- Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor) devices and integrated circuits with them. Background technique [0002] SOI is to introduce a dielectric buried layer between the top semiconductor (called the active layer) and the substrate layer (which can be a semiconductor or insulating medium), and make semiconductor devices or circuits in the active layer. In integrated circuits, high-voltage devices and low-voltage circuits are usually isolated by isolation grooves 30, and between the active layer 3 and the substrate layer 1 are isolated by a dielectric buried layer 2 (such as figure 1 shown). Therefore, compared with bulk silicon technology, SOI technology has the advantages of small parasitic effect...

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Problems solved by technology

Due to the particularity of SOI, its optimization rules will be different, and in the conventional planar gate structure, due to the interaction of the semiconductor buried layer, the gate field plate and the PN junction (the junction of the body region and the drift region), the device The withstand voltage is very sensitive to the position of the semiconductor buried layer, and the process repeatability is very poor (such as Figure 8 shown)

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