Silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with composite dielectric layer and manufacturing method for SiC MOS capacitor with composite dielectric layer

A composite medium and manufacturing method technology, applied in the field of microelectronics, can solve the problems of not improving the reliability of the oxide layer, reducing the interface state density of the device, and the lattice damage of the oxide layer interface, so as to increase the maximum critical electric field and reduce the interface state density , Improve the effect of pressure resistance

Inactive Publication Date: 2011-11-16
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although these two process methods can improve the interface characteristics of the device to a certain extent, there are still some negative effects. For example, the first method cannot control the nitrogen content at the interface, and the process is more difficult.
Although the second method can precisely control the nitrogen content at the interface and effectively reduce the interface state density, the N + The ion implantation process leads to damage to the oxide layer and interface lattice, and the device characteristics a

Method used

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  • Silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with composite dielectric layer and manufacturing method for SiC MOS capacitor with composite dielectric layer
  • Silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with composite dielectric layer and manufacturing method for SiC MOS capacitor with composite dielectric layer

Examples

Experimental program
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Example Embodiment

[0030] Example 1

[0031] Step 1, growing an N-type SiC epitaxial layer.

[0032] The thickness is 380μm, and the doping concentration is 5×10 18 cm -3 The N-type SiC substrate material is placed in a SiC epitaxial growth furnace, the growth temperature is 1570 ℃, the thickness of the growth layer is 10 μm, and the doping concentration is 5×10 15 cm - 3 N-type SiC epitaxial wafer.

[0033] Step 2, pretreating the grown N-type SiC epitaxial wafer.

[0034] 2.1) Ultrasonic cleaning of N-type SiC epitaxial wafers with deionized water;

[0035] 2.2) Clean the SiC epitaxial wafer with 80% sulfuric acid, cook for 10 minutes, and soak for 30 minutes;

[0036] 2.3) Clean the SiC epitaxial wafer several times with deionized water;

[0037] 2.4) Use a ratio of 5:1:1 H 2 O, H 2 O 2 Soak the SiC epitaxial wafer in the mixed solution at a temperature of 80°C for 5 minutes, rinse with hydrofluoric acid solution, rinse with deionized water several times, and finally dry with an infrared lamp.

[0038] St...

Example Embodiment

[0050] Example 2

[0051] Step one is to grow an N-type SiC epitaxial layer.

[0052] The thickness is 380μm, and the doping concentration is 5×10 18 cm -3 The N-type SiC substrate material is placed in a SiC epitaxial growth furnace, the growth temperature is 1570 ℃, the growth layer thickness is 50 μm, and the doping concentration is 2×10 15 cm -3 N-type SiC epitaxial wafer.

[0053] Step two: pretreating the grown N-type SiC epitaxial wafer.

[0054] First, ultrasonically clean the N-type SiC epitaxial wafer with deionized water;

[0055] Next, clean the SiC epitaxial wafer with 80% sulfuric acid, boil it for 10 minutes, and soak it for 30 minutes;

[0056] Next, clean the SiC epitaxial wafer several times with deionized water;

[0057] Then, use a ratio of 5:1:1 H 2 O, H 2 O 2 And hydrochloric acid, soak the SiC epitaxial wafer in the mixed solution at a temperature of 80°C for 5 minutes, wash with a hydrofluoric acid solution, then wash with deionized water several times, and finally...

Example Embodiment

[0070] Example 3

[0071] Step A, N-type SiC epitaxial layer is grown.

[0072] The thickness is 380μm and the doping concentration is 5×10 18 cm -3 The N-type SiC substrate is placed in a SiC epitaxial furnace, the growth temperature is 1600℃, the thickness of the growth layer is 100μm, and the doping concentration is 1×10 15 cm -3 N-type SiC epitaxial layer.

[0073] Step B, pretreatment of the grown N-type SiC epitaxial wafer.

[0074] B1) Ultrasonic cleaning of N-type SiC epitaxial wafer with deionized water;

[0075] B2) Clean the SiC epitaxial wafer with 80% sulfuric acid, cook for 10 minutes, and soak for 30 minutes;

[0076] B3) Clean the SiC epitaxial wafer several times with deionized water;

[0077] B4) H with a ratio of 5:1:1 2 O, H 2 O 2 The SiC epitaxial wafer is immersed in the mixed solution with a temperature of 80°C for 5 minutes, washed with a hydrofluoric acid solution, washed with deionized water several times, and finally dried with an infrared lamp.

[0078] Step C, ...

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Abstract

The invention discloses a silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with a composite dielectric layer, and mainly solves the problem that the conventional SiC MOS capacitor has high interface-state density and weak voltage endurance. The structure of the capacitor is that: an N-type heavy doping SiC substrate layer, an N-type light doping SiC epitaxy layer, an SiO2 transition layer and an HfxAl1-xON dielectric layer are sequentially arranged from bottom to top; the back of the SiC substrate and the surface of the HfxAl1-xON are sputtered with metal Al to form positive and negative electrodes respectively; the N-type SiC epitaxy layer is 10 to 100 mu m thick, the doping concentration is 1*10<15> to 5*10<15>cm<-3>; the SiO2 transition layer is 1 to 15 mu m thick, and the HfxAl1-xON dielectric layer is 10 to 30 mu m thick. The SiO2 transition layer and the HfxAl1-xON layer form a composite dielectric layer structure so as to reduce the interface-state intensity of the dielectric layer and the SiC interface, reduce the current leakage of the dielectric layer, improve the voltage-resisting capability of the dielectric layer, and improve the reliability of the SiC MOS devices. The invention also discloses a manufacturing method for a SiC power integrated circuit and a SiC power isolation device.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and relates to microelectronic devices, in particular to a SiC MOS capacitor with a composite dielectric layer, which can be used in the manufacture of SiC power integrated circuits and SiC power separation devices. Background technique [0002] As a typical representative of the third-generation semiconductor, SiC material has become an ideal material for making high-temperature, high-power, high-frequency and high-radiation-resistant devices due to its excellent physical and chemical properties. Compared with the first-generation semiconductor materials represented by Si and the second-generation semiconductor materials represented by GaAs, SiC materials have the advantages of large band gap, high critical breakdown electric field, and high thermal conductivity. Therefore, SiC materials and devices are currently , Process research and development has become a hot spot in the field of mi...

Claims

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Application Information

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IPC IPC(8): H01L29/94H01L29/51H01L21/02
Inventor 张玉明宋庆文张义门汤晓燕贾仁需王悦湖
Owner XIDIAN UNIV
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