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Optical exposing method, and method for applying optical exposure in preparation of silicon material vertical hollow structure

A silicon material, hollow technology, applied in the direction of microlithography exposure equipment, photosensitive material processing, manufacturing microstructure devices, etc., can solve the problems of expensive, difficult to use, high cost, etc., and achieve low production cost, simple operation and repeatability Good results

Active Publication Date: 2014-11-26
INST OF PHYSICS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The production of such graphics is generally through electron beam exposure or ultraviolet exposure technology, of which electron beam exposure is very expensive and limited in practical application
Using the ordinary UV exposure method, it is necessary to prepare a mask of the same scale, but as we all know, the smaller the pattern size of the mask, the more expensive it is, so it is difficult to use in practice

Method used

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  • Optical exposing method, and method for applying optical exposure in preparation of silicon material vertical hollow structure
  • Optical exposing method, and method for applying optical exposure in preparation of silicon material vertical hollow structure
  • Optical exposing method, and method for applying optical exposure in preparation of silicon material vertical hollow structure

Examples

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Comparison scheme
Effect test

example 1

[0057] For the silicon tubular array structure prepared in this example, please refer to the attached image 3 (a), the silicon tube wall thickness is 200 nanometers, the inner diameter is 300 nanometers, and the height is 20 microns, and its specific preparation method is as follows:

[0058] 1) Silicon wafer surface treatment: take a piece of silicon substrate 1, adopt the conventional semiconductor cleaning process, that is, ultrasonically clean it in acetone, alcohol and deionized water in sequence, and dry it with nitrogen;

[0059] 2) Coating: Spin-coat S1813 photoresist 2 on the silicon substrate 1, and control the spin-coating speed to obtain a photoresist coating with a thickness of 500 nanometers;

[0060] 3) Pre-baking: baking the photoresist-coated silicon wafer obtained in step 2) on a hot plate at 150° C. for 0.5 minutes;

[0061] 4) Exposure: select the mask plate 3 with a solid circle array pattern with a radius of 1 micron. Expose on the MA6 UV exposure mach...

example 2

[0065] For the silicon tubular array structure prepared in this example, please refer to the attached image 3 (b), the silicon tube wall thickness is 100 nanometers, the internal diameter is 350 nanometers, and the height is 20 microns, and its specific preparation method is as follows:

[0066] 1) Silicon wafer surface treatment: take a piece of silicon substrate 1, adopt the conventional semiconductor cleaning process, that is, ultrasonically clean it in acetone, alcohol and deionized water in sequence, and dry it with nitrogen;

[0067] 2) Coating: Spin-coat S1813 photoresist 2 on the silicon substrate 1, and control the spin-coating speed to obtain a photoresist coating with a thickness of 800 nanometers;

[0068] 3) Pre-baking: baking the photoresist-coated silicon wafer obtained in step 2) on a hot plate at 115° C. for 1 minute;

[0069] 4) Exposure: select the mask plate 3 with a solid circle array pattern with a radius of 1 micron. Expose on the MA6 UV exposure mach...

example 3

[0073] For the V-shaped tubular array structure of this example, please refer to the attached image 3 (c), the prepared silicon tube wall thickness is 100 nanometers, the internal diameter is 350 nanometers, and the height is 30 microns, and its specific preparation method is as follows:

[0074] 1) Silicon wafer surface treatment: take a piece of silicon substrate 1, adopt the conventional semiconductor cleaning process, that is, ultrasonically clean it in acetone, alcohol and deionized water in sequence, and dry it with nitrogen;

[0075] 2) Coating: Spin-coat S1813 photoresist 2 on the silicon substrate 1, and control the spin-coating speed to obtain a photoresist coating with a thickness of 800 nanometers;

[0076] 3) Pre-baking: baking the photoresist-coated silicon wafer obtained in step 2) on a hot plate at 115° C. for 1 minute;

[0077] 4) Exposure: select the mask plate 3 with a solid circle array pattern with a radius of 1 micron, and expose it on the MA6 type ultr...

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Abstract

The invention provides an optical exposing method used for forming a micro-nano hollow cavity structure. The method comprises steps that: (1) a mask with a mask pattern is selected, wherein the mask pattern is a geometrical solid pattern or an array thereof with which Poisson spots can be formed through illumination; (2) the mask is positioned above a positive photoresist requiring exposure; exposure is carried out; Poisson spots behind pattern shades are exposed as well; (3) developing is carried out, such that a pattern of hollow cavities corresponding to the Poisson spots is obtained on the positive photoresist. With the method, a silicon pipe-shaped structure array with controllable length-to-diameter ratios can be prepared. With the exposing method, a limit size of laboratory photomask exposure is greatly increased; a limitation of interference exposure that only periodical lines and point lattice can be obtained is broken through; cost is greatly reduced; and experiment technologies are enriched. The structure has a wide application prospect in fields of photonic crystals, filtering devices, and radial p-n junction structured solar cells.

Description

technical field [0001] The invention belongs to the technical field of micro-nano processing, and in particular relates to an optical exposure method and a method for preparing a vertical silicon material hollow structure array. Background technique [0002] Optical exposure is the earliest microfabrication technology used in semiconductor integrated circuits. At present, optical exposure technology is mainly projection exposure technology, and it is mainly an exposure technology for large-scale integrated circuit production. In order to pursue smaller and smaller circuit sizes and as high as possible output, the development of the technology itself is becoming more and more complicated. It requires more and more investment, and the cost is also getting higher and higher. At present, the cost of the most advanced single exposure equipment reaches 20 million to 50 million US dollars, and only a handful of large companies in the world can afford to purchase and The cost of ru...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F7/20G03F7/00G03F7/30B81C1/00
Inventor 顾长志田士兵李俊杰夏晓翔杨海方
Owner INST OF PHYSICS - CHINESE ACAD OF SCI
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