HEMT (high electron mobility transistor) with high breakdown voltage and manufacturing method of HEMT
A manufacturing method and gate electrode technology, applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as device damage, easy breakdown, and device damage, and achieve the goal of improving breakdown voltage and reliability Effect
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Embodiment 1
[0027] First refer to Figure 2a-2d , shows a schematic cross-sectional view of each step of the method for manufacturing a HEMT on a silicon substrate with a high breakdown voltage according to Embodiment 1 of the present invention.
[0028] First, if Figure 2a As shown, a substrate 10 is provided. The material of the substrate 10 may be GaAs, GaN, SiC, sapphire (aluminum oxide), SiGe or Si, etc., or a combination thereof. The substrate 10 can be a thick body substrate, silicon-on-insulator (SOI), generalized SOI structure (semiconductor-insulator-semiconductor, wherein the semiconductor is not limited to silicon), preferably the top of the substrate 10 is a single crystal structure. In consideration of cost control and process compatibility, the present invention preferably uses thick monocrystalline silicon as the substrate 10 . CMP surface treatment can be performed on the substrate 10 to improve its flatness, and deionized water or ultrasonic waves can also be used to...
Embodiment 2
[0034] Refer to the following Figures 4a-4d , shows a schematic cross-sectional view of each step of a method for manufacturing a HEMT on a silicon substrate with a high breakdown voltage according to Embodiment 2 of the present invention.
[0035] First, if Figure 4a As shown, similarly to Embodiment 1, a substrate 10 is provided. The material of the substrate 10 may be GaAs, GaN, SiC, sapphire (aluminum oxide), SiGe or Si, etc., or a combination thereof. The substrate 10 can be a thick body substrate, silicon-on-insulator (SOI), generalized SOI structure (semiconductor-insulator-semiconductor, wherein the semiconductor is not limited to silicon), preferably the top of the substrate 10 is a single crystal structure. In consideration of cost control and process compatibility, the present invention preferably uses thick monocrystalline silicon as the substrate 10 . CMP surface treatment can be performed on the substrate 10 to improve its flatness, and deionized water or ul...
Embodiment 3
[0041] Embodiment 3 is similar to embodiment 2, can refer to appended Figures 4a-4d .
[0042] Firstly, a substrate 10 is provided, and the material may be single crystal silicon.
[0043] Next, a mask 14 is formed on the substrate 10 . For example, the photoresist PR is applied by spin coating on the silicon surface of the substrate 10, and the mask 14 of the photoresist is left on the substrate 10 through exposure and development of the photoresist, and the substrate not covered by the photoresist mask 14 10 surfaces are exposed. In addition, similar to Embodiment 2, a hard mask layer 14 may be formed by photolithography / etching after depositing a silicon nitride material layer, covering part of the substrate 10 and exposing the remaining surface of the substrate 10 .
[0044] Next, different from the thermal oxidation method in Embodiment 2, in Embodiment 3 ion implantation is performed on the exposed substrate 10, and the implanted ion species include oxygen, nitrogen,...
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