[0030] The present invention will be described in detail below in conjunction with the drawings.
[0031] Conventional super junction SOI LDMOS structure, such as figure 1 As shown, 10 is a P-type semiconductor substrate layer. 9 is a silicon dioxide insulating dielectric layer located above the substrate layer 10. The upper end of the silicon dioxide insulating dielectric layer 9 is a P-type body region 4, and the surface of the body region 4 is a P-type body contact region 3 and an N-type source region 2 in sequence. The source electrode S is drawn from the surface of the body contact region 3 and the source region 2. Above the body region 4 is a gate dielectric 6, preferably, the gate dielectric 6 is silicon dioxide, and above the gate dielectric 6 is a conductive material 5. Preferably, the conductive material 5 is formed of polysilicon, and the gate electrode G is drawn from the conductive material 5.
[0032] 7 is an N-type drift region, with a P-type semiconductor region 8 on each side. The two semiconductor regions 8 are symmetric about the drift region 7 and have the same length in the x direction (device lateral direction) as the drift region 7. The drift region 7 And the two semiconductor regions 8 form a super junction structure. Preferably, the sum of the total impurity of the two P-type semiconductor regions 8 (ie the product of the volume and the doping concentration per unit volume) and the total impurity of the N-type drift region 7 should be equal , That is, the charge is balanced, and should be fully exhausted in the blocking state. The drain electrode D is drawn from the surface of the drain region 1.
[0033] Take the N-channel high-k dielectric SOI LDMOS as an example for reference Figure 2a The structure of the semiconductor device of the present invention is explained.
[0034] Figure 2a Shown is an N-channel high-k dielectric SOI LDMOS device provided by the present invention. Its cell structure includes: a silicon dioxide insulating dielectric layer 9, located under the silicon dioxide insulating dielectric layer 9 and insulating from the silicon dioxide. The P-type semiconductor substrate 10 in contact with the layer 9, the device active layer located above the silicon dioxide insulating dielectric layer 9 and in contact with the silicon dioxide insulating dielectric layer 9; the device active layer includes a source region structure, a drain Region structure, gate structure and drift region structure; the source region structure is located on one side of the active layer of the device in the lateral direction (the x direction shown in the figure), including the P-type semiconductor body region 4, which is located on the surface of the P-type semiconductor body region 4 The N+ source region 2 and the P+ contact region 3 are independent of each other. The surface of the N+ source region 2 and the P+ contact region 3 is connected to the metalized source S; the drain region structure is located on the other side of the device active layer in the lateral direction , Including an N+ drain region 1, the surface of the N+ drain region 1 is connected to the metalized drain D; the device active layer between the source region structure and the drain region structure forms a drift region structure, the drift region structure is Two N-type first doped regions 11 parallel to the lateral direction of the device sandwich an N-type second doped region 7 to form a sandwich structure; the outer sides of the two N-type first doped regions 11 each have a layer The high-k dielectric layer 8, the relative dielectric constant of the high-k dielectric layer 8 is greater than the relative dielectric constant of the semiconductor drift region, and the critical breakdown electric field of the high-k dielectric layer 8 is greater than 30V/μm; the gate structure The gate dielectric layer 6 and the gate conductive material 5 constitute a planar gate structure, wherein the gate dielectric layer 6 is located on the surface of the P-type body region 4 and is in contact with part of the N+ source region 2 and part of the drift region structure surface respectively. The polysilicon gate The pole 5 is located on the surface of the gate dielectric layer 6.
[0035] The semiconductor drift region can be semiconductor materials such as semiconductor silicon (k=11.9), germanium (k=16), silicon carbide (k=9.7-10.3), and gallium arsenide (k=13.1).
[0036] Figure 2b It is a schematic diagram of an N-channel high-k dielectric SOI LDMOS structure according to another embodiment of the present invention, which is similar to Figure 2a The difference between the two N-type first doped regions 11 is a P-type second doped region 7 (the two form a super junction structure), and the P-type second doped region 7 is in a blocking state. The high-k dielectric layer 8 collectively depletes the N-type first doped region 11 in the drift zone structure, and the doping concentration of the N-type first doped region 11 can be increased while keeping the device withstand voltage unchanged.
[0037] Figure 2c It is a schematic diagram of an N-channel high-k dielectric SOI LDMOS structure according to another embodiment of the present invention, which is similar to Figure 2a The difference of the embodiment is that the two first semiconductor doped regions 11 and the second semiconductor doped regions 7 in the drift region of the device are both N-type doped regions (the conductivity type and doping concentration of the two are the same). In this case, although the device increases the resistance during forward conduction, the process steps are simplified.
[0038] image 3 It is a schematic diagram of an N-channel high-k dielectric SOI LDMOS structure according to another embodiment of the present invention, which is similar to Figure 2a The difference of the embodiment is that the high-k dielectric layer 8 is not connected to the insulating dielectric layer 9 in the y direction (device longitudinal direction), and a certain distance is reserved between the two. The area between the high-k dielectric layer 8 and the insulating dielectric layer 9 is the second semiconductor doped region 7 (ie N-epitaxial layer). Such a structure can reduce the difficulty of the preparation process of the high-k dielectric layer (preparation of the high-k dielectric layer). The process mainly includes two steps of etching a dielectric groove in the epitaxial layer and filling a high-k dielectric material, where the deeper the etching depth of the dielectric groove, the more difficult the process).
[0039] Figure 4 It is a schematic diagram of an N-channel high-k dielectric SOI LDMOS structure according to another embodiment of the present invention, which is similar to Figure 2a The difference between the two first semiconductor doped regions 11 is that the conductivity type of the two first semiconductor doped regions 11 is N type, the conductivity type of the second semiconductor doped region 7 is P type, and the two N-type first semiconductor doped regions 11 sandwich one The P-type second semiconductor doped region 7 forms a super junction structure, and the high-k dielectric layer 8 and the drift region structure are spaced from the N+ drain region 1 in the x direction, and there is an N-type semiconductor region buffer layer 14 between them. Form a half-height k structure. The introduction of the buffer layer 14 in the N-type semiconductor region can further alleviate the charge imbalance problem caused by the auxiliary depletion of the substrate when the device is reversely blocked.
[0040] Figure 5 It is a schematic diagram of an N-channel high-k dielectric SOI LDMOS structure with a trench gate structure according to another embodiment of the present invention, which is similar to Figure 2a The difference in the embodiment is that the gate structure is a trench gate structure, in which the gate conductive material 5 extends down into the device along both sides of the P-type body region 4 in the device width direction (the z direction in the figure). The source layer and the part extending into the active layer of the device is surrounded by the gate dielectric layer 6, so that the gate dielectric layer 6 is separated between the gate conductive material 5 and the heavy N+ source region 2, the P+ body region 4 and the drift region structure. The trench gate structure forms an additional conductive channel inside the body region 4, which reduces the resistance during forward conduction. Figure 5 On the left is a cross-sectional view of the trench gate structure along the yz plane.
[0041] The structure of the semiconductor device of the present invention is described above by taking an N-channel high-k dielectric SOI LDMOS as an example, and the structure of the present invention is also applicable to a P-channel semiconductor device.
[0042] E.g, Image 6 Shown is P-channel SOI LDMOS, and Figure 2a The structure of SOI LDMOS corresponds only to Figure 2a The N-channel SOI LDMOS becomes P-channel SOI LDMOS, so the conductivity type of each semiconductor region changes accordingly.
[0043] In addition, SOI LDMOS is only an example of the semiconductor device of the present invention. For example, the semiconductor device of the present invention may also include SOI LIGBT. When the conductivity type of the heavily doped semiconductor drain region 1 is the same as the first conductivity type semiconductor body region 4, the lateral SOI power semiconductor device is a lateral IGBT device; when the conductivity type of the heavily doped semiconductor drain region 1 is the same as the first conductivity type When the type semiconductor body region 4 is opposite, the lateral SOI power semiconductor device is a lateral MOS device.
[0044] Figure 7 An N-channel SOI LIGBT according to an embodiment of the present invention is shown. Figure 7 Devices in and Figure 2a The difference between the devices in the main lies in the use of P-type drain region 1 instead Figure 2a In the N-type drain region 1. The structure shown in Figure 2(b), 2(c), 3, 4, 5 or 6 is also applicable to SOI LIGBT.
[0045] The SOI power semiconductor device provided by the present invention reduces the specific on-resistance of the device, improves the withstand voltage of the device, and at the same time reduces the sensitivity of the withstand voltage to charge imbalance, and alleviates the difficulty in conventional super junction SOI LDMOS. Solved substrate assisted depletion effect.
[0046] Pass below Figure 2c The semiconductor device of the present invention and figure 1 The comparison of the conventional super junction SOI LDMOS structure further illustrates the advantages of the present invention:
[0047] 1. Device characteristic analysis
[0048] 1) On-resistance
[0049] On-resistance R of conventional superjunction SOI LDMOS structure on , Mainly by the drift region resistance R D Decided.
[0050] Drift zone resistance R D It is mainly related to the concentration, width, length and current expansion effect of the drift region. Since the SOI power semiconductor device provided by the present invention adopts a high-k medium, the optimized concentration of the N drift region is greater than that of the conventional superjunction SOI LDMOS, which finally leads to a small on-resistance of the proposed structure.
[0051] The structure proposed by the present invention reduces the forward conduction resistance and reduces the power consumption of the device.
[0052] 2) Breakdown voltage
[0053] Compared with conventional super junction SOI LDMOS, the SOI power semiconductor device provided by the present invention has a modulation effect on the internal electric field, which improves the device withstand voltage, and the introduction of high-k dielectric makes the withstand voltage insensitive to charge imbalance. In addition, due to the adaptability of the high-k dielectric to the auxiliary depletion of the N drift region, it effectively alleviates the problem of the substrate-assisted depletion in the conventional super-junction SOI LDMOS resulting in a drop in withstand voltage. In addition, due to the use of high-k dielectrics instead of The P pillar region in the conventional super junction makes the structure process of the present invention relatively simple.
[0054] The above analysis shows that compared with the conventional super junction SOI LDMOS structure, the on-resistance of the SOI power semiconductor device provided by the present invention is reduced, and the withstand voltage is increased. In addition, the SOI power semiconductor device provided by the present invention also has the characteristics of simple manufacturing process, insensitive to the charge imbalance effect, and alleviating the substrate-assisted depletion effect.
[0055] 2. Performance evaluation
[0056] Comprehensive consideration of the impact of various parameters on device performance and consideration of process difficulty, according to Figure 2c Establish the structure model of the SOI power semiconductor device provided by the present invention:
[0057] The length of the high-k medium in the x direction is 10μm, the width in the z direction is 0.5μm, the relative permittivity of the medium is k=200, 500, the length of the N-type drift zone in the x direction is 10μm, and the width in the z direction is 1μm. The corresponding drift zone is optimized Determination of concentration: At this concentration, the withstand voltage and on-resistance of the device reach the best compromise, the thickness of the insulating medium in the y direction is 1 μm, and the thickness of the semiconductor layer on it is 3 μm. Based on this model, Silvaco simulation software is used to simulate the performance of the device.
[0058] 1) Blocking characteristics
[0059] Figure 8-10 Middle N n Indicates the concentration of the N column area, V leak Represents the drain voltage, I leak Represents the drain current, the relative dielectric constant of the medium k=200.
[0060] The relationship between the breakdown voltage of conventional super junction SOI LDMOS and the concentration of the N-type drift region is as follows Picture 8 The curve on the left is shown. The relationship between the breakdown voltage of the semiconductor device of the present invention and the concentration of the N-type drift region is as follows Picture 8 The curve on the right is shown.
[0061] Picture 8 It is shown that when k=200, the optimized concentration of the N-type drift region of the SOI power semiconductor device provided by the present invention is 50% higher than that of the conventional super-junction SOI LDMOS, so the on-resistance and conduction loss are reduced; moreover, the breakdown voltage varies with concentration. The sensitivity of (charge imbalance) is reduced (that is, the curve is smoother), so the process tolerance is greater; furthermore, Picture 9 It is shown that the highest breakdown voltage of the semiconductor device of the present invention is about 30V higher than that of the conventional super junction SOI LDMOS.
[0062] 2) Forward conduction characteristics
[0063] The forward conduction characteristics of the conventional super junction SOI LDMOS and the SOI power semiconductor device provided by the present invention at different k values are as follows: Picture 10 As shown, under a given drain current, the SOI power semiconductor device provided by the present invention has a lower forward voltage drop, and the larger the k value, the better the auxiliary depletion effect on the N-type drift region and the better the optimized concentration Higher, the lower the on-resistance.
[0064] Compared with the conventional super junction SOI LDMOS structure, the SOI power semiconductor device provided by the present invention has a withstand voltage increase of 16% to 18%, a reduction of 13% to 20% compared to the on-resistance, and a device merit (the square of the withstand voltage divided by The specific on-resistance is increased by 62% to 68%; at the same time, the semiconductor device of the present invention has superior performance that is insensitive to charge imbalance, increasing the freedom of device design and manufacturing; secondly, the SOI power semiconductor provided by the present invention The device adopts the process of trenching and refilling the high-k dielectric in the drift zone, which is relatively simple compared with the conventional superjunction process; again, the auxiliary depletion of the high-k dielectric to the drift zone in the SOI power semiconductor device provided by the present invention is adaptive. It alleviates the most common and difficult-to-solve substrate-assisted depletion in conventional super-junction SOI LDMOS, which reduces the withstand voltage. The SOI power semiconductor device provided by the present invention is most suitable for application in the power electronics field with high withstand voltage, low power consumption and easy integration.
