How the transistor is formed

Abstract

A transistor forming method includes the following steps that: a semiconductor substrate with an active region is provided; ion implantation is carried out in the active region so as to forming a doped layer, a P type ion or an N type ion are implanted, a surface of the doped layer is aligned to a surface of the semiconductor substrate; a thermal annealing process is used to activate the doped layer; after the thermal annealing process is used, a dielectric layer and a dummy gate layer are formed on the surface of the doped layer; the dielectric layer covers a lateral wall of the dummy gate layer, the top surface of the dielectric layer is aligned with the top surface of the dummy gate layer; the dielectric layer is used as a mask, the dummy gate layer and the doped layer are etched to penetrate through the doped layer and to expose out of the active region of the semiconductor substrate, so as to form an opening; the bottom of the opening is provided with a semiconductor layer, and a surface of the semiconductor layer is not higher than the surface of the semiconductor substrate; and after the semiconductor layer is formed, the opening is internally provided with a high K metal gate structure. The transistor which is made by the transistor forming method can suppress the leakage current and short channel effect, and can improve the transistor performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits, especially MOS (Metal Oxide Semiconductor, metal-oxide-semiconductor) devices, is continuously reduced to meet the miniaturization and integration of integrated circuit development. requirements. In the process of continuous shrinking of the size of MOS transistor devices, the process of using silicon oxide or silicon oxynitride as the gate dielectric layer in the existing process is challenged. Transistors formed with silicon oxide or silicon oxynitride as the gate dielectric layer have some problems, including increased leakage current and diffusion of impurities, which affect the threshold voltage of the transistor and further affect the performance of semicondu...

AI Technical Summary

Problems solved by technology

[0005] However, transistors with high-K dielectric layers and metal gate structures in the prior art are prone to leakage currents or short channel effects, resulting in poor performance

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