Substrate based bumped flip chip CSP (Chip Scale Package) package part, substrate and manufacturing method

Abstract

The invention discloses a substrate based bumped flip chip CSP (Chip Scale Package) package part, a substrate and a manufacturing method. The package part comprises the substrate and an IC (Integrated Circuit) chip which is inversely installed on the substrate; padding is filled between the substrate and the IC chip; the substrate comprises a substrate middle layer with an upper surface and a lower surface provided with printing lines; the substrate middle layer is provided with a plurality of cylindrical lateral walls which are connected with the printing lines; the upper face and the lower face of the substrate middle layer are provided with substrate bonding pads which are connected with the printing lines. The substrate is manufactured by procedures such as drilling, electrofacing, paving a dry film, exposing and developing with an FR-4 copper-clad plate or a BT substrate serving as substrate raw materials. The CSP package part is obtained by passivating a wafer; forming a UBM layer on the chip bonding pad; coating photoresist; duplicating patterns on a photoresist layer; forming into a stannum / plumbum metal layer; obtaining welding bumped points through backflow; inversely install the chip; melting the welding bumped points; downward filling and obtaining a CSP package part. The package part solves the problems that lead bonding package high-frequency electrical performance is poor and thermal expansion between the ceramic substrate and the PCB is large in mismatch during the existing IC package circuit connection.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging for electronic device manufacturing, and relates to a bump flip-chip CSP package based on a substrate; the invention also relates to a substrate used in the package, and the invention further relates to a package of the package Manufacturing method. Background technique [0002] With the increasing development of electronic information technology, integrated circuit packaging is developing towards high performance on the one hand, and developing towards thinner and smaller on the other hand. In IC packaging, the connection between the chip and the substrate (lead frame) provides a circuit connection for the distribution of power and signals. There are three ways to realize the internal connection of the IC chip package: wire bonding, automatic welding and flip chip weld. At present, more than 90% of the IC chip connection methods are still wire bonding. Due to the long bonding wi...

AI Technical Summary

Problems solved by technology

However, after the silicon chip (silicon die) is installed on the ceramic substrate, the thermal expansion coefficient (CTE) of the ceramic substrate and the PCB substrate do not match and the difference is too large (the CTE of the ceramic substrate is 6-8ppm / ℃, and the CTE of the PCB substrate is 16~19ppm / ℃), it is difficult to place the ceramic substrate on the PCB substrate

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